Chapter4 SignalConnections
6023E/6024E/6025EUser Manual 4-42 ni.com
As anoutput, theUPDATE* signal reflects the actual update pulse that is
connected to the DACs.This is true even if the updates are externally
generated byanother PFI. Th eo utput is an activelow pulse with a pulse
width of 300 to 350 ns. This output is set to high impedance at startup.
Figures 4-32 and 4-33 show the input and output timing requirements for
the UPDATE*signal.
Figure4-32. UPDATE* Input Signal Timing
Figure4-33. UPDATE* Output Signal Timing
The DACsare updated within 100 ns of the leading edge. Separate the
UPDATE*pulseswith enough time that new data can be written to the DAC
latches.
Thedevice UI counter normally generates the UPDATE*signal unless you
select some externalsource. The UI counter is started by the WFTRIG
signalan d can be stopped bysoftware or the internal Buffer Counter.
D/A conversionsgenerated by either an internal or external UPDATE*
signald o not occur when gated bythe software command register gate.
UISOURCE Signal
Any PFIpin can ext ernally input the UISOURCE signal, which is not
available as an output on the I/O connector. The UI counter uses the
UISOURCE signal as a clockt o time the generation of the UPDATE*
Rising-Edge
Polarity
Falling-Edge
Polarity
tw
tw=10 ns minimum
tw
tw=300-350 ns