Chapter4 SignalConnections
6023E/6024E/6025EUser Manual 4-48 ni.com
leave the DIO7pi n freefor gene raluse. Fig ure 4-41 shows the timing
requirementsfor the GATE and SOURCE input signals and the timing
specifications for the OUT output signals of your device.
Figure4-41. GPCTRTiming Summary
TheGATE and OUT signal transitions shownin Figure 4-41arereferenced
tothe rising edge of the SOURCE signal. This timing diagram assumes that
the counters are programmed to count rising edges. The same timing
diagram,but with the source signal inverted and referenced to the falling
edgeof the source signal, applies when the counter is programmed to count
fallingedges.
The GATEinput timing parameters are referenced to the signal at the
SOURCEinput or to one of the internally generated signals on your device.
Figure 4-41 showsthe GATE signal referenced to the rising edge of a
sourcesignal. The gate must be valid (either high or low) for at least 10 ns
beforethe rising or falling edge of a source signal for the gate to take effect
atthat source edge, as shown by tgsu and tgh in Figure 4-41. The gate signal
is not requiredto be held after the active edge of the source signal.
SOURCE VIH
VIL
VIH
VIL
tsc tsp
tgsu tgh
tgw
GATE
tout
OUT VOH
VOL
sc
t
t
t
t
t
t 50ns minimum
sp 23ns minimum
gsu 10ns minimum
gh 0ns minimum
gw 10ns minimum
out 80ns maximum
SourceClock Period
SourcePulse Width
GateSetup Time
GateHold Time
GatePulse Width
OutputDelay Time
tsp