SCC General Information | Quatech MPAP-100 guide

9 SCC General Information

The Serial Communications Controller (SCC) is a dual channel, multi-protocol data communications peripheral. The MPAP-100 provides a single channel for communications, however, portions of the second channel can be utilized to support some special circumstances. The SCC can be configured to satisfy a wide variety of serial communications applications. Some of its protocol capabilities include:

SDLC/HDLC (Bit Synchronous) Communications

Abort sequence generation and checking

Automatic zero insertion and deletion

Automatic flag insertion between messages

Address field recognition

I-field residue handling

CRC generation and detection

SDLC loop mode with EOP recognition/loop entry and exit

Byte-oriented Synchronous Communications

Internal/external character synchronization

1 or 2 sync characters in separate registers

Automatic Cyclic Redundancy Check (CRC) generation/detection

Asynchronous Communications

5, 6, 7, or 8 bits per character

1, 1-1/2, or 2 stop bits

Odd, even, or no parity

Times 1, 16, 32, or 64 x clock modes

Break generation and detection

Parity, overrun and framing error detection

NRZ, NRZI, or FM encoding/decoding

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Quatech MPAP-100 user manual SCC General Information, SDLC/HDLC Bit Synchronous Communications, Asynchronous Communications

Contents

Users Manual MPAP-100 RS-232 PCMCIA SYNCHRONOUS ADAPTERfor PCMCIA Card Standard compatible machines QUATECH, INC MPAP-100 WARRANTY INFORMATIONPRODUCT DESCRIPTION Single Channel PCMCIA RS-232-D Synchronous Communications Adapter Copyright 2001 Quatech, Inc 5.3 OS/2 Client Driver Configuration Examples 5.2.1 Tying a configuration to a particular socket5.4 Monitoring The Status Of PCMCIA Cards Table of Contents 10.3.1 Using channel A for both transmit and receive Table of ContentsAccessing the SCC while FIFOs are enabled 22.1.4 Older Versions of Card and Socket Services 1.1 System Requirements 1 Introduction 2 Hardware Installation 3 DOS / Windows 3.x Software Installation DEVICE=drive\path\MPAP1CL.SYS S#,B#,I#,C ... S#,B#,I#,C 3.1.1 DOS client driver installation3.1 MPAP-100 Client Driver for DOS 3.1.3 Hot Swapping 3.1.2 Auto Fallback configurationPage DEVICE=C\MPAP-100\MPAP1CL.SYS 3.2 DOS Client Driver examplesDEVICE=C\MPAP-100\MPAP1CL.SYS b300,c DEVICE=C\MPAP-100\MPAP1CL.SYS s0,b300,i5 3.3.1 DOS Enabler Installation 3.3 MPAP-100 Enabler for DOS3.3.3 Configuring a card 3.3.2 Hot Swapping is not supported MPAP1EN S#,B#,I#,W#,C MPAP1EN S#,R,W# 3.3.4 Releasing a cards configuration MPAP1EN.EXE s0,b300,i5,c 3.4 DOS Enabler ExamplesMPAP1EN.EXE s1,b300,i3,wd8 MPAP1EN.EXE s0,r 4.1 Using the Add New Hardware Wizard 4 Windows 95/98 InstallationPage Page 4.2 Viewing Resources with Device Manager 4.3 Configuration Options 5.2 OS/2 Client Driver Installation 5 OS/2 Software Installation5.1 System Requirements DEVICE=drive\path\MPAP100.SYS addr,irq,C ... addr,irq,C 5.2.3 Hot Swapping 5.2.2 Auto Fallback configuration DEVICE=C\MPAP-100\MPAP100.SYS 300,5 5.5 Installing OS/2 PCMCIA SupportPage 6 Using the MPAP-100 with Syncdrive 7 Addressing 8 Interrupts SDLC/HDLC Bit Synchronous Communications 9 SCC General InformationByte-oriented Synchronous Communications Asynchronous Communications 9.1 Accessing the registers Example 3 Write data into the transmit buffer of channel A coding, CRC reset Master interrupt control and resetInterrupt control, Wait/DMA request control Interrupt vector 9.3 SCC Data Encoding Methods 9.2 Baud Rate Generator Programming9.4 Support for SCC Channel B ClockFrequency TimeConst 2 BaudRate ClockMode 9.4.4 Other signals are not used 9.4.1 Receive data and clock signals9.4.2 Extra clock support for channel A 9.4.3 Extra handshaking for channel A 9.5.2 Software Interrupt Acknowledge 9.5 SCC Incompatibility Warnings9.5.1 Register Pointer Bits 10 FIFO Operation 10.2 Accessing the FIFOs10.1 Enabling and disabling the FIFOs 10.2.1 Transmit FIFO 10.2.2 Receive FIFO 10.3 SCC configuration for FIFO operation Register 10.3.2 Using channel B for receive 10.4.1 Interrupt status 10.4 FIFO status and control 10.5 Accessing the SCC while FIFOs are enabled 10.4.2 Resetting the FIFOs10.4.3 Reading current FIFO status 10.4.4 Controlling the FIFOsPage 10.7 Receive FIFO timeout SWSYNC 11 Communications Register Bits 1-0 Reserved, always RCKEN --- Receive Clock SourceBit 2 TCKEN --- Transmit Clock Source INTS1, INTS0 --- Interrupt Source and Enable Bits 12 Configuration RegisterFIFOEN --- External data FIFO enable External Data FIFOs Present --- Reserved, always RXSRC --- Receive FIFO DMA Source 13 Interrupt Status Register 14 FIFO Status Register 15 FIFO Control Register Bits 7-0 Receive Pattern CharacterThis is 16 Receive Pattern Character Register Bits 7-0 Receive Pattern Count 17 Receive Pattern Count Register Bit 7 X16MODE --- Clock Mode 18 Receive FIFO Timeout RegisterBit 6 Reserved, always Bits 5-0 Timeout Interval 19 External Connections 19.2 RING pin 19.1 SYNCA pin 19.3 Null-modem cables CIRCUIT AB - SIGNAL GROUND 20 DTE Interface SignalsCIRCUIT BB - RECEIVED DATA CIRCUIT CB - CLEAR TO SEND CIRCUIT CD - DTE READY DATA TERMINAL READY CONNECTOR NOTATION DTR CIRCUIT CC - DCE READY DATA SET READY CONNECTOR NOTATION DSRCIRCUIT CE - RING INDICATOR CONNECTOR NOTATION RING CIRCUIT CF - RECEIVED LINE SIGNAL DETECT CARRIER DETECT CIRCUIT TM - TEST MODE 21 Specifications 22.1.3 Multiple Configuration Attempts 22 Software Troubleshooting22.2 DOS Enabler 22.1 DOS Client Driver 22.1.1 Generic SuperClient Drivers 22.2.2 Socket Numbers 22.2.1 With Card and Socket Services22.2.3 Memory range exclusion 22.3 OS/2 Client Driver 22.3.1 Resources Not AvailablePage MPAP-100 Users Manual Revision March P/N