Quatech MPAP-100 user manual Addressing

7 Addressing

The MPAP-100 occupies a continuous 16-byte block of I/O addresses. For example, if the base address is set to 300 hex, then the MPAP-100 will occupy address locations 300 hex to 30F hex. If the computer in which the MPAP-100 is installed is running PCMCIA Card and Socket Services, the base address is set by the client driver. If PCMCIA Card and Socket Services are not being used, the base address is set by the MPAP-100 enabler program.

The first four bytes of address space on the MPAP-100 contain the internal registers of the SCC. Other Quatech architecture-specific registers occupy eight more bytes. The remainder of the address space is reserved for future use. The MPAP-100 address map is shown in Table 2.

Address		Register Description
Base + 0		SCC Data Port, Channel A
Base + 1		SCC Control Port, Channel A
Base + 2		SCC Data Port, Channel B
Base + 3		SCC Control Port, Channel B
Base + 4		Communications Register
Base + 5		Configuration Register
Base + 6		Reserved
Base + 7		Reserved
Base + 8		Interrupt Status Register
Base + 9		FIFO Status Register
Base + A		FIFO Control Register
Base + B		Receive Pattern Character Register
Base + C		Receive Pattern Count Register
Base + D		Receive FIFO Timeout Register
Base + E		Reserved
Base + F		Reserved
	Table 2 --- MPAP-100 Address Assignments

Information on the internal registers of the SCC can be found in Table 3 and Table 4 and in the technical reference manuals available from Zilog. The other onboard registers are fully described in subsequent chapters of this manual.