Quatech MPAP-100 user manual Interrupt Status Register

13 Interrupt Status Register

The Interrupt Status Register is used to determine the cause of an interrupt generated by the MPAP-100. The address of this register is Base+8. Table 11 details the bit definitions of the register. The interrupt source in the Configuration Register (see page 41) must be set to INTSCC for any of the statuses indicated by this register to occur. This register can be ignored if the external FIFOs are not being used.

	Bit 7		Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
	0		0	0	0	RX_PAT	RX_FIFO	TX_FIFO	SCC
			Table 11 --- Interrupt Status Register - Read Only/Write Clear
Bits 7-4:		Reserved, always 0.
Bit 3:		RX_PAT --- Receive Pattern Interrupt:								The
		receive pattern interrupt occurs when the character set in the Receive Pattern
		Character Register is detected 'n' consecutive times in the received data stream,
		where 'n' is the value set in the Receive Pattern Count Register. This bit is set
		(logic 1) to indicate the interrupt. It remains set until cleared by writing a '1' to
		this bit.
Bit 2:		RX_FIFO --- Receive FIFO Interrupt:
		The receive FIFO interrupt occurs when the number of bytes held in the external
		receive FIFO rises above the half-full mark, or when a receive FIFO timeout
		occurs. This bit is set (logic 1) to indicate the interrupt. It remains set until
		cleared by writing a '1' to this bit.
Bit 1:		TX_FIFO --- Transmit FIFO Interrupt:								The
		transmit FIFO interrupt occurs when the number of bytes held in the external
		transmit FIFO falls below the half-full mark. This bit is set (logic 1) to indicate
		the interrupt. It remains set until cleared by writing a '1' to this bit.
Bit 0:		SCC --- SCC Interrupt:
		If this bit is set (logic 1), the SCC has generated an interrupt. Software should
		clear the interrupt condition by performing appropriate service on the SCC. This
		bit is not latched.