Communications Register, Swsync | Quatech MPAP-100 guide

11 Communications Register

11 Communications Register

The Communications Register is used to set options pertaining to the clocks. The source and type of clock to be transmitted or received can be specified. External synchronization and RS-232 DTE test modes and can also be controlled with this register. The address of the Communications Register is Base+4. Table 9 details its bit definitions.

	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2		Bit 1	Bit 0
				RLEN
	TM ST	EXTSYNC	LLEN	or	RCKEN	TCKEN		0	0
				SW_SYNC
		Table 9 --- Communications Register - Read/Write
Bit 7:	TM ST --- Test Mode Status:
	This bit can be used to read the status of the Test Mode signal on a DTE, allowing
	the user to monitor the signal without generating any interrupts.
Bit 6:	EXTSYNC --- External Sync Enable:
	If this bit is set (logic 1), software-controlled sync is disabled and the SCC's
	SYNCA input is driven by the signal coming on pin 10 of the DB-25 connector.
Bit 5: LLEN --- Local Loopback Enable:									When set
	(logic 1), this bit allows the DTE to test the functioning of the DTE/DCE interface
	and the transmit and receive sections of the local DCE. The DCE device must
	support local loopback for this to work. When cleared (logic 0), no testing occurs.
	LLEN can also be used as a software-controlled general-purpose output.
Bit 4: RLEN --- Remote Loopback Enable:									SW_SYNC
	--- Software Sync On:									When

the 'C' option is used with the client driver or enabler, this bit functions as SW_SYNC, otherwise it functions as RLEN.

RLEN

('C' option not used)If this bit is set (logic 1), the DTE can test the transmission path through the remote DCE to the remote DTE interface and the return transmission path. The remote device must support remote loopback for this to work. When cleared (logic 0), no testing occurs.

SW_SYNC ('C' option is used)

This bit is used to drive the active-low SYNC input of the channel A receiver. The SYNC signal is asserted when this bit is set (logic 1), and is deasserted when this bit is clear (logic 0). This is useful in situations where it is necessary to

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Quatech MPAP-100 user manual Communications Register, Swsync

Contents

MPAP-100 RS-232 PCMCIA SYNCHRONOUS ADAPTER Users Manualfor PCMCIA Card Standard compatible machines QUATECH, INC WARRANTY INFORMATION MPAP-100PRODUCT DESCRIPTION Single Channel PCMCIA RS-232-D Synchronous Communications Adapter Copyright 2001 Quatech, Inc 5.2.1 Tying a configuration to a particular socket 5.3 OS/2 Client Driver Configuration Examples5.4 Monitoring The Status Of PCMCIA Cards Table of Contents Table of Contents 10.3.1 Using channel A for both transmit and receiveAccessing the SCC while FIFOs are enabled 22.1.4 Older Versions of Card and Socket Services 1 Introduction 1.1 System Requirements 2 Hardware Installation 3 DOS / Windows 3.x Software Installation DEVICE=drive\path\MPAP1CL.SYS S#,B#,I#,C ... S#,B#,I#,C 3.1.1 DOS client driver installation3.1 MPAP-100 Client Driver for DOS 3.1.2 Auto Fallback configuration 3.1.3 Hot SwappingPage 3.2 DOS Client Driver examples DEVICE=C\MPAP-100\MPAP1CL.SYSDEVICE=C\MPAP-100\MPAP1CL.SYS b300,c DEVICE=C\MPAP-100\MPAP1CL.SYS s0,b300,i5 3.3 MPAP-100 Enabler for DOS 3.3.1 DOS Enabler Installation3.3.3 Configuring a card 3.3.2 Hot Swapping is not supported MPAP1EN S#,B#,I#,W#,C 3.3.4 Releasing a cards configuration MPAP1EN S#,R,W# 3.4 DOS Enabler Examples MPAP1EN.EXE s0,b300,i5,cMPAP1EN.EXE s1,b300,i3,wd8 MPAP1EN.EXE s0,r 4 Windows 95/98 Installation 4.1 Using the Add New Hardware WizardPage Page 4.2 Viewing Resources with Device Manager 4.3 Configuration Options 5 OS/2 Software Installation 5.2 OS/2 Client Driver Installation5.1 System Requirements DEVICE=drive\path\MPAP100.SYS addr,irq,C ... addr,irq,C 5.2.2 Auto Fallback configuration 5.2.3 Hot Swapping 5.5 Installing OS/2 PCMCIA Support DEVICE=C\MPAP-100\MPAP100.SYS 300,5Page 6 Using the MPAP-100 with Syncdrive 7 Addressing 8 Interrupts 9 SCC General Information SDLC/HDLC Bit Synchronous CommunicationsByte-oriented Synchronous Communications Asynchronous Communications 9.1 Accessing the registers Example 3 Write data into the transmit buffer of channel A Master interrupt control and reset coding, CRC resetInterrupt control, Wait/DMA request control Interrupt vector 9.2 Baud Rate Generator Programming 9.3 SCC Data Encoding Methods9.4 Support for SCC Channel B ClockFrequency TimeConst 2 BaudRate ClockMode 9.4.1 Receive data and clock signals 9.4.4 Other signals are not used9.4.2 Extra clock support for channel A 9.4.3 Extra handshaking for channel A 9.5.2 Software Interrupt Acknowledge 9.5 SCC Incompatibility Warnings9.5.1 Register Pointer Bits 10.2 Accessing the FIFOs 10 FIFO Operation10.1 Enabling and disabling the FIFOs 10.2.1 Transmit FIFO 10.3 SCC configuration for FIFO operation 10.2.2 Receive FIFO Register 10.3.2 Using channel B for receive 10.4 FIFO status and control 10.4.1 Interrupt status 10.4.2 Resetting the FIFOs 10.5 Accessing the SCC while FIFOs are enabled10.4.3 Reading current FIFO status 10.4.4 Controlling the FIFOsPage 10.7 Receive FIFO timeout 11 Communications Register SWSYNC Bits 1-0 Reserved, always RCKEN --- Receive Clock SourceBit 2 TCKEN --- Transmit Clock Source 12 Configuration Register INTS1, INTS0 --- Interrupt Source and Enable BitsFIFOEN --- External data FIFO enable External Data FIFOs Present --- Reserved, always RXSRC --- Receive FIFO DMA Source 13 Interrupt Status Register 14 FIFO Status Register 15 FIFO Control Register 16 Receive Pattern Character Register Bits 7-0 Receive Pattern CharacterThis is 17 Receive Pattern Count Register Bits 7-0 Receive Pattern Count Bit 7 X16MODE --- Clock Mode 18 Receive FIFO Timeout RegisterBit 6 Reserved, always Bits 5-0 Timeout Interval 19 External Connections 19.1 SYNCA pin 19.2 RING pin 19.3 Null-modem cables 20 DTE Interface Signals CIRCUIT AB - SIGNAL GROUNDCIRCUIT BB - RECEIVED DATA CIRCUIT CB - CLEAR TO SEND CIRCUIT CC - DCE READY DATA SET READY CONNECTOR NOTATION DSR CIRCUIT CD - DTE READY DATA TERMINAL READY CONNECTOR NOTATION DTRCIRCUIT CE - RING INDICATOR CONNECTOR NOTATION RING CIRCUIT CF - RECEIVED LINE SIGNAL DETECT CARRIER DETECT CIRCUIT TM - TEST MODE 21 Specifications 22 Software Troubleshooting 22.1.3 Multiple Configuration Attempts22.2 DOS Enabler 22.1 DOS Client Driver 22.1.1 Generic SuperClient Drivers 22.2.1 With Card and Socket Services 22.2.2 Socket Numbers22.2.3 Memory range exclusion 22.3 OS/2 Client Driver 22.3.1 Resources Not AvailablePage MPAP-100 Users Manual Revision March P/N