Using channel B for receive | Quatech MPAP-100 guide

10.3.2 Using channel B for receive

10.3.2 Using channel B for receive

The MPAP-100 supplies only limited support for SCC channel B. This mode, therefore, is not recommended for most applications. Set RXSRC (bit 1) in the Configuration Register to logic 1. This will configure the MPAP-100 to use W/REQA for transmit DMA and W/REQB for receive DMA. In addition to any other desired SCC configuration, ensure that the following bits are set according to Table 7:

	Register	Bit(s)	Value	Function
				Enable DMA request on W/REQA. This bit
		7	1	should be set after the other bits in WR1 are set as
	WR1A			desired.
	WR1A	6	1	Set W/REQA for DMA Request mode.
		6	1	Set W/REQA for DMA Request mode.
		5	0	Use W/REQA for transmit.
		1	0	Disable transmit interrupts.

WR14A

2

0

Disable DMA request-on-transmit on DTR/REQA.

WR15A

0

1

Enable WR7A'.

WR7A'

5

0

Assert transmit DMA request when entry location of internal FIFO is empty.

WR1B

Enable DMA request on W/REQB. This bit

71 should be set after the other bits in WR1 are set as desired.

	6	1	Set W/REQB for DMA Request mode.
	5	1	Use W/REQB for receive.
	4-3	11 or	Enable receive interrupts on special conditions
	4-3	00	only (recommended), or disable them completely.
		00	only (recommended), or disable them completely.

Table 7 --- Configuring the SCC for Rx DMA on channel B

Image 39

Quatech MPAP-100 user manual Using channel B for receive

Contents

QUATECH, INC MPAP-100 RS-232 PCMCIA SYNCHRONOUS ADAPTERUsers Manual for PCMCIA Card Standard compatible machines Synchronous Communications Adapter WARRANTY INFORMATIONMPAP-100 PRODUCT DESCRIPTION Single Channel PCMCIA RS-232-D Copyright 2001 Quatech, Inc Table of Contents 5.2.1 Tying a configuration to a particular socket5.3 OS/2 Client Driver Configuration Examples 5.4 Monitoring The Status Of PCMCIA Cards 22.1.4 Older Versions of Card and Socket Services Table of Contents10.3.1 Using channel A for both transmit and receive Accessing the SCC while FIFOs are enabled 1.1 System Requirements 1 Introduction 2 Hardware Installation 3 DOS / Windows 3.x Software Installation 3.1.1 DOS client driver installation 3.1 MPAP-100 Client Driver for DOSDEVICE=drive\path\MPAP1CL.SYS S#,B#,I#,C ... S#,B#,I#,C 3.1.3 Hot Swapping 3.1.2 Auto Fallback configurationPage DEVICE=C\MPAP-100\MPAP1CL.SYS s0,b300,i5 3.2 DOS Client Driver examplesDEVICE=C\MPAP-100\MPAP1CL.SYS DEVICE=C\MPAP-100\MPAP1CL.SYS b300,c 3.3.2 Hot Swapping is not supported 3.3 MPAP-100 Enabler for DOS3.3.1 DOS Enabler Installation 3.3.3 Configuring a card MPAP1EN S#,B#,I#,W#,C MPAP1EN S#,R,W# 3.3.4 Releasing a cards configuration MPAP1EN.EXE s0,r 3.4 DOS Enabler ExamplesMPAP1EN.EXE s0,b300,i5,c MPAP1EN.EXE s1,b300,i3,wd8 4.1 Using the Add New Hardware Wizard 4 Windows 95/98 InstallationPage Page 4.2 Viewing Resources with Device Manager 4.3 Configuration Options DEVICE=drive\path\MPAP100.SYS addr,irq,C ... addr,irq,C 5 OS/2 Software Installation5.2 OS/2 Client Driver Installation 5.1 System Requirements 5.2.3 Hot Swapping 5.2.2 Auto Fallback configuration DEVICE=C\MPAP-100\MPAP100.SYS 300,5 5.5 Installing OS/2 PCMCIA SupportPage 6 Using the MPAP-100 with Syncdrive 7 Addressing 8 Interrupts Asynchronous Communications 9 SCC General InformationSDLC/HDLC Bit Synchronous Communications Byte-oriented Synchronous Communications 9.1 Accessing the registers Example 3 Write data into the transmit buffer of channel A Interrupt vector Master interrupt control and resetcoding, CRC reset Interrupt control, Wait/DMA request control ClockFrequency TimeConst 2 BaudRate ClockMode 9.2 Baud Rate Generator Programming9.3 SCC Data Encoding Methods 9.4 Support for SCC Channel B 9.4.3 Extra handshaking for channel A 9.4.1 Receive data and clock signals9.4.4 Other signals are not used 9.4.2 Extra clock support for channel A 9.5 SCC Incompatibility Warnings 9.5.1 Register Pointer Bits9.5.2 Software Interrupt Acknowledge 10.2.1 Transmit FIFO 10.2 Accessing the FIFOs10 FIFO Operation 10.1 Enabling and disabling the FIFOs 10.2.2 Receive FIFO 10.3 SCC configuration for FIFO operation Register 10.3.2 Using channel B for receive 10.4.1 Interrupt status 10.4 FIFO status and control 10.4.4 Controlling the FIFOs 10.4.2 Resetting the FIFOs10.5 Accessing the SCC while FIFOs are enabled 10.4.3 Reading current FIFO statusPage 10.7 Receive FIFO timeout SWSYNC 11 Communications Register RCKEN --- Receive Clock Source Bit 2 TCKEN --- Transmit Clock SourceBits 1-0 Reserved, always External Data FIFOs Present --- Reserved, always 12 Configuration RegisterINTS1, INTS0 --- Interrupt Source and Enable Bits FIFOEN --- External data FIFO enable RXSRC --- Receive FIFO DMA Source 13 Interrupt Status Register 14 FIFO Status Register 15 FIFO Control Register Bits 7-0 Receive Pattern CharacterThis is 16 Receive Pattern Character Register Bits 7-0 Receive Pattern Count 17 Receive Pattern Count Register 18 Receive FIFO Timeout Register Bit 6 Reserved, always Bits 5-0 Timeout IntervalBit 7 X16MODE --- Clock Mode 19 External Connections 19.2 RING pin 19.1 SYNCA pin 19.3 Null-modem cables CIRCUIT CB - CLEAR TO SEND 20 DTE Interface SignalsCIRCUIT AB - SIGNAL GROUND CIRCUIT BB - RECEIVED DATA CIRCUIT CF - RECEIVED LINE SIGNAL DETECT CARRIER DETECT CIRCUIT CC - DCE READY DATA SET READY CONNECTOR NOTATION DSRCIRCUIT CD - DTE READY DATA TERMINAL READY CONNECTOR NOTATION DTR CIRCUIT CE - RING INDICATOR CONNECTOR NOTATION RING CIRCUIT TM - TEST MODE 21 Specifications 22.1 DOS Client Driver 22.1.1 Generic SuperClient Drivers 22 Software Troubleshooting22.1.3 Multiple Configuration Attempts 22.2 DOS Enabler 22.3 OS/2 Client Driver 22.3.1 Resources Not Available 22.2.1 With Card and Socket Services22.2.2 Socket Numbers 22.2.3 Memory range exclusionPage MPAP-100 Users Manual Revision March P/N