Quatech MPAP-100 Configuration Register, External Data FIFOs Present --- Reserved, always, Bits

12 Configuration Register

The Configuration Register is used to set the interrupt source and enable the interface between the SCC and the external FIFOs. The address of this register is Base+5. Table 10 details the bit definitions of the register.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

0

INTS1

INTS0

0

FIFOEN

RXSRC

0

Table 10 --- Configuration Register - Read/Write

Bit 7:

External Data FIFOs Present --- Reserved, always 1.

This

bit can be used as an indicator that external data FIFOs are present. Other

MPA-series products that are not equipped with external data FIFOs, including

MPAP-100 Revision A cards, will return 0 in this bit location.

Bit 6:

Reserved, always 0.

Bits 5-4:

INTS1, INTS0 --- Interrupt Source and Enable Bits:

These

two bits determine the source of the interrupt. The two sources are interrupt from

the SCC (INTSCC), and interrupt on Test Mode (INTTM). Only one interrupt

source can be active at a time. Below is the mapping for these bits. Note that

FIFO-related interrupts will occur only when INTSCC is chosen.

INTS1

INTS0

Interrupt Source

0

0

Interrupts disabled

0

0

reserved

1

0

INTSCC

1

1

INTTM

Bit 3: Reserved, always 0.

Bit 2:

FIFOEN --- External data FIFO enable:

If this

bit is set (logic 1), the external data FIFOs are enabled. If this bit is clear (logic

0), the external data FIFOs are disabled. (See page 31 for full details on FIFO

use.)