Quatech MPAP-100 user manual RXSRC --- Receive FIFO DMA Source, Reserved, always

Bit 1:	RXSRC --- Receive FIFO DMA Source:				This
	bit determines which SCC pins are used to control transmit and receive DMA
	transactions between the SCC and the external FIFOs (when enabled). The
	transmit data FIFO is always used with SCC channel A. The receive data FIFO
	may be used with SCC channel A by setting RXSRC to logic 0, or with SCC
	channel B by setting RXSRC to logic 1. (See page 29 for information on using
	channel B.)
			RXSRC = 0	RXSRC = 1
		Receive DMA	W/REQA	W/REQB
		Transmit	DTR/REQA	W/REQA
		DMA
Bit 0:	Reserved, always 0.