MPAP1EN S#,B#,I#,W#,C | Quatech MPAP-100 guide

The enabler requires a single desired configuration to be provided on the command line. The card will not be configured if the desired configuration is not provided. The desired configuration must be enclosed in parentheses and it contains parameters separated using commas (no spaces). In the descriptions below, replace the '#' symbols with the appropriate numeric values.

	MPAP1EN (S#,B#,I#,W#,C)
S#	The PCMCIA socket into which the MPAP-100 will be inserted. This value is a
	decimal number ranging from 0 to 15. This parameter is always required when
	configuring a card.
B#	The base I/O address of the MPAP-100. This number must be a three-digit
	hexadecimal value ending in 0. This parameter is always required when
	configuring a card.
I#	The interrupt level (IRQ) of the MPAP-100. This decimal number must be one of
	the following values: 3, 4, 5, 7, 9, 10, 11, 12, 14, 15, or 0 if no IRQ is desired.
	This parameter is always required when configuring a card.
W#	(optional) The base address of the memory window used by the enabler. This
	two-digit hexadecimal number can be one of the following values: C8, CC, D0
	(default), D4, D8, or DC. Use D4 for a memory window at segment D400, D8 for
	a memory window at segment D800, etc. If this parameter is omitted, the default
	setting of D000 will be used.

C(optional) Drive SYNC input of SCC channel A with the Remote Loopback bit of Communications Register (see page 39). If this parameter is omitted, the SYNC input of SCC channel A will be undefined.

Image 14

Quatech MPAP-100 user manual MPAP1EN S#,B#,I#,W#,C

Contents

for PCMCIA Card Standard compatible machines MPAP-100 RS-232 PCMCIA SYNCHRONOUS ADAPTERUsers Manual QUATECH, INC PRODUCT DESCRIPTION Single Channel PCMCIA RS-232-D WARRANTY INFORMATIONMPAP-100 Synchronous Communications Adapter Copyright 2001 Quatech, Inc 5.4 Monitoring The Status Of PCMCIA Cards 5.2.1 Tying a configuration to a particular socket5.3 OS/2 Client Driver Configuration Examples Table of Contents Accessing the SCC while FIFOs are enabled Table of Contents10.3.1 Using channel A for both transmit and receive 22.1.4 Older Versions of Card and Socket Services 1 Introduction 1.1 System Requirements 2 Hardware Installation 3 DOS / Windows 3.x Software Installation DEVICE=drive\path\MPAP1CL.SYS S#,B#,I#,C ... S#,B#,I#,C 3.1.1 DOS client driver installation3.1 MPAP-100 Client Driver for DOS 3.1.2 Auto Fallback configuration 3.1.3 Hot SwappingPage DEVICE=C\MPAP-100\MPAP1CL.SYS b300,c 3.2 DOS Client Driver examplesDEVICE=C\MPAP-100\MPAP1CL.SYS DEVICE=C\MPAP-100\MPAP1CL.SYS s0,b300,i5 3.3.3 Configuring a card 3.3 MPAP-100 Enabler for DOS3.3.1 DOS Enabler Installation 3.3.2 Hot Swapping is not supported MPAP1EN S#,B#,I#,W#,C 3.3.4 Releasing a cards configuration MPAP1EN S#,R,W# MPAP1EN.EXE s1,b300,i3,wd8 3.4 DOS Enabler ExamplesMPAP1EN.EXE s0,b300,i5,c MPAP1EN.EXE s0,r 4 Windows 95/98 Installation 4.1 Using the Add New Hardware WizardPage Page 4.2 Viewing Resources with Device Manager 4.3 Configuration Options 5.1 System Requirements 5 OS/2 Software Installation5.2 OS/2 Client Driver Installation DEVICE=drive\path\MPAP100.SYS addr,irq,C ... addr,irq,C 5.2.2 Auto Fallback configuration 5.2.3 Hot Swapping 5.5 Installing OS/2 PCMCIA Support DEVICE=C\MPAP-100\MPAP100.SYS 300,5Page 6 Using the MPAP-100 with Syncdrive 7 Addressing 8 Interrupts Byte-oriented Synchronous Communications 9 SCC General InformationSDLC/HDLC Bit Synchronous Communications Asynchronous Communications 9.1 Accessing the registers Example 3 Write data into the transmit buffer of channel A Interrupt control, Wait/DMA request control Master interrupt control and resetcoding, CRC reset Interrupt vector 9.4 Support for SCC Channel B 9.2 Baud Rate Generator Programming9.3 SCC Data Encoding Methods ClockFrequency TimeConst 2 BaudRate ClockMode 9.4.2 Extra clock support for channel A 9.4.1 Receive data and clock signals9.4.4 Other signals are not used 9.4.3 Extra handshaking for channel A 9.5.2 Software Interrupt Acknowledge 9.5 SCC Incompatibility Warnings9.5.1 Register Pointer Bits 10.1 Enabling and disabling the FIFOs 10.2 Accessing the FIFOs10 FIFO Operation 10.2.1 Transmit FIFO 10.3 SCC configuration for FIFO operation 10.2.2 Receive FIFO Register 10.3.2 Using channel B for receive 10.4 FIFO status and control 10.4.1 Interrupt status 10.4.3 Reading current FIFO status 10.4.2 Resetting the FIFOs10.5 Accessing the SCC while FIFOs are enabled 10.4.4 Controlling the FIFOsPage 10.7 Receive FIFO timeout 11 Communications Register SWSYNC Bits 1-0 Reserved, always RCKEN --- Receive Clock SourceBit 2 TCKEN --- Transmit Clock Source FIFOEN --- External data FIFO enable 12 Configuration RegisterINTS1, INTS0 --- Interrupt Source and Enable Bits External Data FIFOs Present --- Reserved, always RXSRC --- Receive FIFO DMA Source 13 Interrupt Status Register 14 FIFO Status Register 15 FIFO Control Register 16 Receive Pattern Character Register Bits 7-0 Receive Pattern CharacterThis is 17 Receive Pattern Count Register Bits 7-0 Receive Pattern Count Bit 7 X16MODE --- Clock Mode 18 Receive FIFO Timeout RegisterBit 6 Reserved, always Bits 5-0 Timeout Interval 19 External Connections 19.1 SYNCA pin 19.2 RING pin 19.3 Null-modem cables CIRCUIT BB - RECEIVED DATA 20 DTE Interface SignalsCIRCUIT AB - SIGNAL GROUND CIRCUIT CB - CLEAR TO SEND CIRCUIT CE - RING INDICATOR CONNECTOR NOTATION RING CIRCUIT CC - DCE READY DATA SET READY CONNECTOR NOTATION DSRCIRCUIT CD - DTE READY DATA TERMINAL READY CONNECTOR NOTATION DTR CIRCUIT CF - RECEIVED LINE SIGNAL DETECT CARRIER DETECT CIRCUIT TM - TEST MODE 21 Specifications 22.2 DOS Enabler 22 Software Troubleshooting22.1.3 Multiple Configuration Attempts 22.1 DOS Client Driver 22.1.1 Generic SuperClient Drivers 22.2.3 Memory range exclusion 22.2.1 With Card and Socket Services22.2.2 Socket Numbers 22.3 OS/2 Client Driver 22.3.1 Resources Not AvailablePage MPAP-100 Users Manual Revision March P/N