Quatech MPAP-100 user manual SYNCA pin, RING pin

N/C 13		25	TM (OUTPUT)
N/C	12
		24	TxCLK (DTE)
RxCLK (DTE)11
		23	N/C
SYNCA	10
		22	RING
N/C 9
		21	RLBK (OUTPUT)
CD	8
DGND	7	20	DTR
		19	N/C
DSR	6
		18	LLBK (OUTPUT)
CTS	5
		17	RxCLK (DCE)
RTS	4
		16	N/C
RxD	3
		15	TxCLK (DCE)
TxD	2
CGND	1	14	N/C

Figure 2 --- MPAP-100 Output Connector

The testing signals the DTE can generate are Local Loopback (LL) and Remote Loopback (RL). These signals are asserted with certain bits in the Communications Register. When a Test Mode (TM) condition is received from the DCE, an interrupt can optionally be generated.

19.1 SYNCA (pin 10)

If EXTSYNC (bit 6) in the Communications Register is set to a logic 1, the SYNCA signal from the connector is used to drive the active-low SYNC input of SCC channel A. The signal is inverted by the RS-232 receiver, so a positive voltage on pin 10 will assert SYNCA. The SCC must be specifically programmed to recognize external synchronization.

19.2 RING (pin 22)

If Card and Socket Services has set the SIGCHG bit in the PCMCIA Configuration Status Register to a logic 1, the RING signal is routed to the STSCHG line on the PCMCIA bus. The signal is inverted by the RS-232 receiver, so a positive voltage on pin 22 will assert STSCHG.

Table 17 shows the pin configuration of the MPAP-100 DTE connector. The definitions of the interchange circuits according to the RS-232-D standard can be found starting on page 52.

Pin

To

DTE

From

DTE

Signal

RS-232-D

Circuit

SCC Pin or Register Bit