Quatech MPAP-100 user manual FIFO Status Register

14 FIFO Status Register

The FIFO Status Register is used to return current status information about the external FIFOs. The address of this read-only register is Base+9. Table 12 details the bit definitions of the register. This register can be ignored if the external FIFOs are not being used.

	Bit 7		Bit 6		Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
	0		RXF		RXH	RXE	0	TXF	TXH	TXE
				Table 12 --- FIFO Status Register - Read Only
Bit 7:		Reserved, always 0.
Bit 6:		RXF --- Receive FIFO Full:									This
		bit is set (logic 1) when the external receive FIFO is completely full. The FIFO
		will accept no more data from the SCC.
Bit 5:		RXH --- Receive FIFO Half Full:									This
		bit is set (logic 1) while the external receive FIFO is at least half-full.
Bit 4:		RXE --- Receive FIFO Empty:
		This bit is set (logic 1) when the external receive FIFO is completely empty.
Bit 3:		Reserved, always 0.
Bit 2:		TXF --- Transmit FIFO Full:
		This bit is set (logic 1) when the external transmit FIFO is completely full.
		Further writes to the external transmit FIFO will be ignored.
Bit 1:		TXH --- Transmit FIFO Half Full:									This

bit is set (logic 1) while the external transmit FIFO is at least half-full.

Bit 0: TXE --- Transmit FIFO Empty:

This bit is set (logic 1) when the external transmit FIFO is completely empty.