A
BOUT
THE
T
IGER
S
TACK
III 10/1001-2
Figure 1-1 Front and Rear Panels.
Switch Architecture
The switch employs a wire-speed, non-blocking switching fabric. This
permits simultaneous wire-speed transport of multiple packets at low
latency on all ports. The switch also features full-duplex capability on all
ports, which effectively doubles the bandwidth of each connection.
The switch uses store-and-forward s witching to ensure maximum data
integrity. With store-and-forward switching, the entire packet must be
received into a buffer and checked for validity before being forwarded.
This prevents errors from being propagated throughout the network.
This switch includes two Gigabit combination ports with RJ-45
connectors and associated SFP slots. The optional SFP stacking transceiver
enables up to eight units to be connected together throu gh a 1 Gbps stack
backplane. The switch stack can be managed from a master unit usin g a
single IP address.
Power-over-Ethernet Capability
The switch’s 24 10/100 Mbps ports support the IEEE 802.3af
Power-over-Ethernet (PoE) standard that enables DC power to be
supplied to attached devices using wires in the connecting Ethernet cable.
Any 802.3af compliant device attached to a port can directly draw power
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10 11 12 13 14 15 16 17 18 1920 21 22 2324
26
Console
25
1
2
11
12
13
14
23
24
PowerSocket
ConsolePort 10/100Mbps RJ-45 Ports CombinationPort
StatusIndicators (25, 26) ModePoE/LinkButton
PortStatus Indicators (1-24)
CombinationRJ-45/SFP Ports
SystemIndicators
StackMaster Button
RedundantPower Socket
RPS
DCIN
+12V 7.5A
-50V 7.5A
100-240V~
50/60Hz8.0-2.0A
Link/Act
PoE
25
26
Pwr
Diag
Stack Mode
PoE/Link
RPS