SUPER MICRO Computer C2SBA+II, C2SBE Chipset Overview, Graphic Memory Controller Hub Gmch

C2SBA+II/C2SBA+/C2SBA/C2SBE User’s Manual

1-2 Chipset Overview

The Intel G33/P35 chipset is specially designed for use with the Intel dual core processors. It consists of two primary components: the Graphic Memory Controller Hub (GMCH) and the I/O Controller Hub (ICH9/ICH9R). The GMCH (North Bridge) manages the data flow between the CPU interface (FSB), the System Memory interface, the External Graphics interface, and the I/O Controller through the DMI (Direct Media) Interface. The ICH9/ICH9R (South Bridge) provides a multitude of I/O related functions.

Graphic Memory Controller Hub (GMCH)

Utilizing a single LGA 775 socket processor, the G33/P35 GMCH supports an FSB frequency of 1.33 GHz/1.06 GHz. Host-initiated I/O cycles are decoded to the PCI- Express, the DMI, or the GMCH configuration space. Host-initiated memory cycles are decoded to PCI-Express, DMI or system memory. The GMCH supports 36-bit host bus addressing and a Cache Line Size of 64 bytes.

The GMCH supports one or two channels of DDR2 memory with up to two DIMMs per channel with a maximum bandwidth of 6.4 GB/s in asymmetric mode or 12.8 GB/s in symmetric mode using DDR2 800 MHz memory. It also supports an op- portunistic refresh scheme, a memory thermal management scheme and Partial Writes to Memory using Data Mask (DM) signals.

The GMCH contains one PCI-Express x16 (16-lane) port intended for an external PCI-Express graphics card that is compatible with the PCI Express Base Specifica- tion revision 1.1. This PCI-E x16 port runs at a frequency of 2.5 GB/s on each lane and supports a maximum theoretical bandwidth of 40 GB/s in each direction for an aggregate of 8 GB/s @ x16. It supports traditional PCI-/AGP- style traffic and a PCI-Exp. Enhanced Addressing Mechanism with advanced capabilities in automatic discovery, negotiation and training of link out of reset.

Providing the high-speed, chip-to-chip connection between the GMCH and ICH9/ ICH9R is the Direct Media Interface (DMI). The DMI integrates advanced priority- based servicing, allowing for concurrent traffic, true isochronous transfer capabilities and permitting current as well as legacy software to function seamlessly.

Intel ICH9/ICH9R System Features

The Intel 9th Generation I/O Controller Hub (ICH9/ICH9R) supports a variety of I/O related functions and PCI devices, including the following:

•DMI-to PCI Bridge

•LPC Controller

•Thermal Subsystem

•SMBus Controller

•USB FS/LS UHCI Controllers #1, #2 and #3

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