SMI and NMI Routing
There are numerous SMI sources and all are routed to the PIIX4. Software must configure the PIIX4 SMI source pins to control whether SMI is propagated through to the processor via its H_SMI input or not. For details on the fault conditions that cause SMI to occur, consult the data sheets of the SMI source ICs. The SMI routing on the server board is described in Table 6. Note that some PIIX4 inputs have several sources. Schematic signal names are in parenthesis.
Table 6. SMI and NMI Routing
SMI Source
BX Chipset PCI SERR# - used for ECC Errors (P_SERR#)
LAN PCI SERR# (P_SERR#)
All three PCI Slot’s SERR# (P_SERR#)
Gluechips EXTSMI# output – used for +5 VSB errors
Gluechips EXTSMI# output – Through buffer to (P_SERR#)
LAN1 PCI PME# (P_PME#)
LAN2 PCI PME# (P_PME#)
All three PCI slot’s PME# (P_PME#)
Super I/O Serial Interrupt SMI – used for watchdog timer (SER_IRQ)
Super I/O PME# (SIO_RIA#) – originally from WOR header or ext. modem
Wake on LAN header – used for Wake on LAN (WOL#)
PIIX4 Input Pin
EXT_SMI#
EXT_SMI#
EXT_SMI#
GPI13
EXT_SMI#
GPI1
GPI1
GPI1
SER_IRQ
RIAB
LID
The Gluechips EXT_SMI# output is also connected to the PIIX4 GPI13 pin to provide a status of the Gluechips EXT_SMI# signal.
All NMI generation on the server board is under software control. Writes to PIIX4 GPO17 are routed to the PIIX4 IOCHK# input which may be configured to cause a NMI to occur. Thus, software may cause a NMI to occur by pulsing GPO17 active.
The TR440BX server board BIOS SMI handler detects SMI events, logs the events, and elevates selected events to NMI level.
Power Connector
When used with an
Speaker
A
Description | 19 |