Intel 41110 manual Package Information, Package Specification

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Package Information

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3.1Package Specification

The 41110 Bridge is in a 567-ball FCBGA package, 31mm X 31mm in size, with a 1.27mm ball pitch (see Figure 5 and Figure 6).

Figure 5. 41110 Bridge Package Dimensions (Top View)

Handling			Die
Exclusion		0. 491in.	Keepout
Area	0.	291in.	Area
	0.	291in.
0. 547in. 0. 247in.			17. 00mm 21. 00mm 31. 00mm
0.	200in.
		17. 00mm
		21. 00mm
		31. 00mm

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Contents Design Guide Intel 41110 Serial to Parallel PCI BridgeIntel 41110 Serial to Parallel PCI Bridge Design Guide Contents Tables FiguresContents Date Revision Description March 001 Initial release Revision HistoryTerm Definition About This DocumentTerminology and Definitions Terminology and Definitions Sheet 1Terminology and Definitions Sheet 2 About This DocumentPCI Express Interface Features PCI-X Interface FeaturesIntroduction2 Introduction Power ManagementSMBus for configuration register initialization SMBus InterfaceMicrocontroller Connections to Microcontroller Block DiagramRelated Documents JtagIntel 41110 Serial to Parallel PCI Bridge Applications Block DiagramAdapter Card Block Diagram Package Information Package SpecificationPackage Information Bridge Package Dimensions Side View41110 Decoupling Guidelines Power Plane LayoutPower Plane Layout 300 Split Voltage PlanesDecoupling Guidelines 41110PCI Reset and Power Timing Considerations5 ARST# and PERST# Timing RequirementsVCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk General Routing Guidelines EMI ConsiderationsPower Distribution and Decoupling Trace ImpedanceDecoupling Cross Section of Differential Trace Differential ImpedanceBoard Layout Guidelines Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Adapter Card Stackup Board Layout GuidelinesINTx Routing Table AINT# Interrupt Pins PCI Express INTx MessagePCI-X Layout Guidelines InterruptsInterrupt Binding for Devices Behind a Bridge PCI ArbitrationInterrupt Routing for Devices Behind a Bridge PCI-X Layout GuidelinesPCI Resistor Compensation PCI General Layout GuidelinesPCI/PCI-X Frequency/Mode Straps PCI-X SignalsPCI Clock Layout Guidelines PCI Pullup Resistors Not RequiredPCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements SummaryPCI-X Topology Layout Guidelines 41110 Layout AnalysisPCI-X Slot Guidelines Embedded PCI-X 133 MHz Embedded PCI-X 133 MHz Routing RecommendationsParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHzPCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI 66 MHz Embedded TopologyPCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode TopologyGeneral recommendations PCI Express LayoutAdapter Card Routing Recommendations Sheet 1 PCI-Express Layout GuidelinesAdapter Card Layout Guidelines PCI Express LayoutAdapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations ConfigCircuit Implementations 10.1 41110 Analog Voltage FiltersPCI Express Analog Voltage Filter PCI Analog Voltage FiltersPCI Express Analog Voltage Filter Circuit Bandgap Analog Voltage FilterBandgap Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation PinsSMBUs Address Configuration SM BusBit Value This page intentionally left blank CRB Board Stackup Sheet 1 Layer Type Thickness Copper WeightCustomer Reference Boards Board Stack-upCRB Board Stackup Sheet 2 MaterialImpedance Customer Reference BoardsMechanical Outline Board OutlineThis page intentionally left blank PERCOMP10 Design Guide ChecklistPCI Express Interface Signals Signals Recommendations Reason/ImpactPCI/PCI-X Interface Signals Sheet 1 Design Guide ChecklistMiscellaneous Signals PCI/PCI-X Interface Signals Sheet 2Recommendations Reason/Impact SMBus Interface SignalsBallout Pin Name Usage Reset PinsSignal Recommendations Reason/Impact Power and Ground SignalsJtag Signals This page intentionally left blank