Intel 41110 manual About This Document, Terminology and Definitions Sheet 1, Term Definition

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About This Document

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This document provides layout information and guidelines for designing platform or add-in board applications with the Intel® 41110 Serial to Parallel PCI Bridge (also called the 41110 Bridge). It is recommended that this document be used as a guideline. Intel recommends employing best-known design practices with board level simulation, signal integrity testing and validation for a robust design.

Designers should note that this guide focuses upon specific design considerations for the 41110 Bridge and is not intended to be an all-inclusive list of all good design practices. Use this guide as a starting point and use empirical data to optimize your particular design.

1.1Terminology and Definitions

Table 1 provides a list of terms and definitions that may be useful when working with the 41110 Bridge product.

Table 1. Terminology and Definitions (Sheet 1 of 2)

Term

 

 

 

 

Definition

 

 

 

 

 

 

 

 

 

 

 

 

 

Stripline in a PCB is composed of the

 

 

 

 

 

 

conductor inserted in a dielectric with GND

 

 

 

 

 

 

planes to the top and bottom.

Stripline

 

 

 

 

 

NOTE: An easy way to distinguish stripline

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

from microstrip is that you need to

 

 

 

 

 

 

strip away layers of the board to view

 

 

 

 

 

 

 

 

 

 

 

 

the trace on stripline.

 

 

 

 

 

 

 

 

 

 

 

 

 

Microstrip in a PCB is composed of the

 

 

 

 

 

 

Microstrip

 

 

 

 

 

conductor on the top layer above the dielectric

 

 

 

 

 

 

with a ground plane below

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Material used for the lamination process of manufacturing PCBs. It consists of a layer of

Prepreg

epoxy material that is placed between two cores. This layer melts into epoxy when heated and

 

forms around adjacent traces.

 

 

 

 

 

 

Core

Material used for the lamination process of manufacturing PCBs. This material is two sided

laminate with copper on each side. The core is an internal layer that is etched.

 

 

 

 

 

 

 

 

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Contents Design Guide Intel 41110 Serial to Parallel PCI BridgeIntel 41110 Serial to Parallel PCI Bridge Design Guide Contents Tables FiguresContents Date Revision Description March 001 Initial release Revision HistoryTerm Definition About This DocumentTerminology and Definitions Terminology and Definitions Sheet 1Terminology and Definitions Sheet 2 About This DocumentPCI-X Interface Features PCI Express Interface FeaturesIntroduction2 Introduction Power ManagementSMBus for configuration register initialization SMBus InterfaceMicrocontroller Connections to Microcontroller Block DiagramRelated Documents JtagIntel 41110 Serial to Parallel PCI Bridge Applications Block DiagramAdapter Card Block Diagram Package Information Package SpecificationPackage Information Bridge Package Dimensions Side View41110 Decoupling Guidelines Power Plane LayoutPower Plane Layout 300 Split Voltage PlanesDecoupling Guidelines 41110PCI ARST# and PERST# Timing Requirements Reset and Power Timing Considerations5VCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk General Routing Guidelines EMI ConsiderationsTrace Impedance Power Distribution and DecouplingDecoupling Cross Section of Differential Trace Differential ImpedanceAdapter Card Topology Board Layout GuidelinesAdapter Card Stack Up, Microstrip and Stripline Adapter Card Stackup Board Layout GuidelinesINTx Routing Table AINT# Interrupt Pins PCI Express INTx MessagePCI-X Layout Guidelines InterruptsInterrupt Binding for Devices Behind a Bridge PCI ArbitrationInterrupt Routing for Devices Behind a Bridge PCI-X Layout GuidelinesPCI Resistor Compensation PCI General Layout GuidelinesPCI/PCI-X Frequency/Mode Straps PCI-X SignalsPCI Clock Layout Guidelines PCI Pullup Resistors Not RequiredPCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements Summary41110 Layout Analysis PCI-X Topology Layout GuidelinesPCI-X Slot Guidelines Embedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 133 MHzParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHzPCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI 66 MHz Embedded TopologyPCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode TopologyGeneral recommendations PCI Express LayoutAdapter Card Routing Recommendations Sheet 1 PCI-Express Layout GuidelinesAdapter Card Layout Guidelines PCI Express LayoutAdapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations ConfigCircuit Implementations 10.1 41110 Analog Voltage FiltersPCI Express Analog Voltage Filter PCI Analog Voltage FiltersPCI Express Analog Voltage Filter Circuit Bandgap Analog Voltage FilterBandgap Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation PinsSM Bus SMBUs Address ConfigurationBit Value This page intentionally left blank CRB Board Stackup Sheet 1 Layer Type Thickness Copper WeightCustomer Reference Boards Board Stack-upCRB Board Stackup Sheet 2 MaterialImpedance Customer Reference BoardsMechanical Outline Board OutlineThis page intentionally left blank PERCOMP10 Design Guide ChecklistPCI Express Interface Signals Signals Recommendations Reason/ImpactPCI/PCI-X Interface Signals Sheet 1 Design Guide ChecklistMiscellaneous Signals PCI/PCI-X Interface Signals Sheet 2Recommendations Reason/Impact SMBus Interface SignalsBallout Pin Name Usage Reset PinsSignal Recommendations Reason/Impact Power and Ground SignalsJtag Signals This page intentionally left blank