Intel 41110 manual PCI Express Layout, General recommendations

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PCI Express Layout

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This section provides an overview of the PCI-Express stackup recommended based on Intel presimulation results. For additional information, refer to the Intel® 41110 Serial to Parallel PCI Bridge Developer’s Manual or the PCI Express Specification, Revision 1.0 from the www.pcisig.com website.

9.1General recommendations

PCI Express is a serial differential low-voltage point-to-point interconnect. The PCI Express was designed to support 20 inches between components with standard FR4. The 41110 supports x8 lanes. PCI-Express requires special considerations be made for interconnect losses, jitter, crosstalk and mode conversions. The below list provides some general guidelines for the layout of a PCI-Express trace:

1.Jitter: Trace lengths of a PCB trace can introduce around 1 to 5 ps of jitter and 0.35 to 0.5 dB of loss per inch of differential pair. An add-in card the trace length from edge-finger pad to device is limited to 3 inches.

2.Matching within pair: Trace lengths of matching differential pairs are required to be matched within +/-5 mil delta. Each net within a differential pair should be length matched on a segment-by-segment basis at point of discontinuity such as an breakout area, routes between vias, routes between AC coupling capacitors and connector pins.

3.Trace Symmetry: Trace Symmetry is required between two traces of the same differential pair.

4.Vias: Vias contribute 0.5 to 1.0 dB/via toward the loss budget. Vias on an add-in card should be limited to one near the breakout section of the pads and one near the edge finger.

5.Bends: Trace bends should be kept to a minimum. If bends are used they should be at a 45- degree angle or smaller. The number of left and right bends should be matched as closely as possible to even out the overall lengths of each segment of the differential pair.

6.AC Coupling capacitors: AC coupling capacitor with a value of 75nF to 200nF should line up at the same location from one trace to the other within the pair. The 0402 size capacitor with a small pad size is highly recommended. The breakout from the capacitor should be symmetrical for both signal traces in the differential pair.

7.Connector pins: Length compensation for the connector pins of the differential pair being offset from each other the PCB trace should be considered.

8.Ground Plane Referencing: Ground plane referencing is required along the entire route of the differential pair. Traces routed near the edge should maintain a 40 mil air gap to the edge. Layer switching should also maintain the ground plane. Grounds between planes should be connected with stitching vias (with one to three recommended per differential pair).

9.Breakout Areas: Breakout areas near a device package should be limited to 500 mils in lengths. The necking down to a smaller trace width should be symmetrical on the differential pair.

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Contents Design Guide Intel 41110 Serial to Parallel PCI BridgeIntel 41110 Serial to Parallel PCI Bridge Design Guide Contents Tables FiguresContents Date Revision Description March 001 Initial release Revision HistoryTerminology and Definitions About This DocumentTerminology and Definitions Sheet 1 Term DefinitionTerminology and Definitions Sheet 2 About This DocumentIntroduction2 PCI Express Interface FeaturesPCI-X Interface Features SMBus for configuration register initialization Power ManagementSMBus Interface IntroductionMicrocontroller Connections to Microcontroller Block DiagramRelated Documents JtagIntel 41110 Serial to Parallel PCI Bridge Applications Block DiagramAdapter Card Block Diagram Package Information Package SpecificationPackage Information Bridge Package Dimensions Side View41110 Decoupling Guidelines Power Plane LayoutPower Plane Layout Decoupling Guidelines Split Voltage Planes41110 300PCI VCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations5ARST# and PERST# Timing Requirements Reset and Power Timing Considerations Crosstalk General Routing GuidelinesGeneral Routing Guidelines General Routing Guidelines EMI ConsiderationsDecoupling Power Distribution and DecouplingTrace Impedance Cross Section of Differential Trace Differential ImpedanceAdapter Card Stack Up, Microstrip and Stripline Board Layout GuidelinesAdapter Card Topology Adapter Card Stackup Board Layout GuidelinesPCI-X Layout Guidelines AINT# Interrupt Pins PCI Express INTx MessageInterrupts INTx Routing TableInterrupt Routing for Devices Behind a Bridge PCI ArbitrationPCI-X Layout Guidelines Interrupt Binding for Devices Behind a BridgePCI Resistor Compensation PCI General Layout GuidelinesPCI Clock Layout Guidelines PCI-X SignalsPCI Pullup Resistors Not Required PCI/PCI-X Frequency/Mode StrapsPCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements SummaryPCI-X Slot Guidelines PCI-X Topology Layout Guidelines41110 Layout Analysis Parameter Routing Guideline for Lower AD Bus Embedded PCI-X 133 MHzEmbedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHzPCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI 66 MHz Embedded TopologyPCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode TopologyGeneral recommendations PCI Express LayoutAdapter Card Layout Guidelines PCI-Express Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations Config10.1 41110 Analog Voltage Filters Circuit ImplementationsPCI Express Analog Voltage Filter PCI Analog Voltage FiltersPCI Express Analog Voltage Filter Circuit Bandgap Analog Voltage FilterBandgap Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation PinsBit Value SMBUs Address ConfigurationSM Bus This page intentionally left blank Customer Reference Boards Layer Type Thickness Copper WeightBoard Stack-up CRB Board Stackup Sheet 1Impedance MaterialCustomer Reference Boards CRB Board Stackup Sheet 2Mechanical Outline Board OutlineThis page intentionally left blank PCI Express Interface Signals Design Guide ChecklistSignals Recommendations Reason/Impact PERCOMP10PCI/PCI-X Interface Signals Sheet 1 Design Guide ChecklistMiscellaneous Signals PCI/PCI-X Interface Signals Sheet 2Recommendations Reason/Impact SMBus Interface SignalsBallout Pin Name Usage Reset PinsSignal Recommendations Reason/Impact Power and Ground SignalsJtag Signals This page intentionally left blank