Intel 41110 manual PCI/PCI-X Interface Signals Sheet 2, Miscellaneous Signals

Page 57

 

 

 

Design Guide Checklist

Table 20. PCI/PCI-X Interface Signals (Sheet 2 of 2)

 

 

 

 

 

 

Signals

Recommendations

Reason/Impact

 

 

 

 

 

 

Controls frequency of the PCI segment when running

 

 

 

in conventional PCI mode (33 MHz or 66 MHz):

 

 

A_M66EN

0 = 33 MHz PCI

 

 

1 = 66 MHz PCI

Sampled on the rising edge of

 

 

Pull-up using a 8.2Kresistor when the PCI bus is

PERST#.

 

 

 

 

 

to operate at 66 MHz and not already pulled up by

 

 

 

system board. This signal is grounded for 33 MHz

 

 

 

operation.

 

 

 

 

 

 

 

 

Design without secondary PCI/PCI-

 

 

 

X Slot

 

 

 

— If there is at least one legacy

 

 

 

PCI device on the PCI/PCI-X

 

 

 

bus, tie this pin directly to

 

 

 

GND.

 

 

 

— If all devices are PCI-X

 

 

 

capable and there is at least

 

 

 

one PCI-X device that only

 

A_PCIXCAP

Connects directly to the PCIXCAP pin on the PCI slot.

supports maximum PCI-X

 

66MHz on the secondary PCI

 

 

bus, pull down to GND

 

 

Connect to VCC33 through an 8.2K pullup resistor.

through 10Kseries resistor

 

 

 

parallel with a 0.01uF

 

 

 

capacitor.

 

 

 

— If all secondary PCI-X

 

 

 

devices (and the bus loading)

 

 

 

support PCI-X 133MHz,

 

 

 

connect PCIXCAP to 3.3V

 

 

 

through an 8.2K resistor

 

 

 

 

 

 

The series resistor on IDSEL should be 200±5% if it

 

 

IDSEL

is exclusively PCIX mode. If it is PCI mode or mixed

 

 

PCI/ PCIX mode is intended, 510 ohms is

 

 

 

 

 

 

recommended.

 

 

 

 

 

Table 21. Miscellaneous Signals

Signals

Recommendations

Reason/Impact

 

 

 

RSTIN#

Used for debug purposes. Connect to VCC33 through

 

an 8.2Kpullup resistor for normal operation.

 

 

 

 

 

 

A_STRAP0,

 

 

A_STRAP1,

These signals REQUIRE external pull-downs to GND

 

A_STRAP2,

 

on the board 8.2Kunless otherwise stated.

 

A_STRAP6,

 

 

 

RESERVED [8:1]

 

 

 

 

 

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Contents Design Guide Intel 41110 Serial to Parallel PCI BridgeIntel 41110 Serial to Parallel PCI Bridge Design Guide Contents Tables FiguresContents Date Revision Description March 001 Initial release Revision HistoryTerminology and Definitions About This DocumentTerminology and Definitions Sheet 1 Term DefinitionTerminology and Definitions Sheet 2 About This DocumentPCI Express Interface Features PCI-X Interface FeaturesIntroduction2 SMBus for configuration register initialization Power ManagementSMBus Interface IntroductionMicrocontroller Connections to Microcontroller Block DiagramRelated Documents JtagIntel 41110 Serial to Parallel PCI Bridge Applications Block DiagramAdapter Card Block Diagram Package Information Package SpecificationPackage Information Bridge Package Dimensions Side View41110 Decoupling Guidelines Power Plane LayoutPower Plane Layout Decoupling Guidelines Split Voltage Planes41110 300PCI Reset and Power Timing Considerations5 ARST# and PERST# Timing RequirementsVCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk General Routing Guidelines EMI ConsiderationsPower Distribution and Decoupling Trace ImpedanceDecoupling Cross Section of Differential Trace Differential ImpedanceBoard Layout Guidelines Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Adapter Card Stackup Board Layout GuidelinesPCI-X Layout Guidelines AINT# Interrupt Pins PCI Express INTx MessageInterrupts INTx Routing TableInterrupt Routing for Devices Behind a Bridge PCI ArbitrationPCI-X Layout Guidelines Interrupt Binding for Devices Behind a BridgePCI Resistor Compensation PCI General Layout GuidelinesPCI Clock Layout Guidelines PCI-X SignalsPCI Pullup Resistors Not Required PCI/PCI-X Frequency/Mode StrapsPCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements SummaryPCI-X Topology Layout Guidelines 41110 Layout AnalysisPCI-X Slot Guidelines Embedded PCI-X 133 MHz Embedded PCI-X 133 MHz Routing RecommendationsParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHzPCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI 66 MHz Embedded TopologyPCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode TopologyGeneral recommendations PCI Express LayoutAdapter Card Layout Guidelines PCI-Express Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations Config10.1 41110 Analog Voltage Filters Circuit ImplementationsPCI Express Analog Voltage Filter PCI Analog Voltage FiltersPCI Express Analog Voltage Filter Circuit Bandgap Analog Voltage FilterBandgap Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation PinsSMBUs Address Configuration SM BusBit Value This page intentionally left blank Customer Reference Boards Layer Type Thickness Copper WeightBoard Stack-up CRB Board Stackup Sheet 1Impedance MaterialCustomer Reference Boards CRB Board Stackup Sheet 2Mechanical Outline Board OutlineThis page intentionally left blank PCI Express Interface Signals Design Guide ChecklistSignals Recommendations Reason/Impact PERCOMP10PCI/PCI-X Interface Signals Sheet 1 Design Guide ChecklistMiscellaneous Signals PCI/PCI-X Interface Signals Sheet 2Recommendations Reason/Impact SMBus Interface SignalsBallout Pin Name Usage Reset PinsSignal Recommendations Reason/Impact Power and Ground SignalsJtag Signals This page intentionally left blank