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| Design Guide Checklist |
Table 20. |
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| Signals | Recommendations | Reason/Impact |
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| Controls frequency of the PCI segment when running |
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| in conventional PCI mode (33 MHz or 66 MHz): |
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| A_M66EN | 0 = 33 MHz PCI |
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| 1 = 66 MHz PCI | Sampled on the rising edge of | |
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| • | PERST#. |
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| to operate at 66 MHz and not already pulled up by |
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| system board. This signal is grounded for 33 MHz |
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| operation. |
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| • Design without secondary PCI/PCI- |
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| X Slot |
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| — If there is at least one legacy |
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| PCI device on the |
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| bus, tie this pin directly to |
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| GND. |
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| — If all devices are |
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| capable and there is at least |
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| one |
| A_PCIXCAP | Connects directly to the PCIXCAP pin on the PCI slot. | supports maximum |
| 66MHz on the secondary PCI | ||
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| Ω | bus, pull down to GND |
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| Connect to VCC33 through an 8.2K pullup resistor. | through 10KΩ series resistor |
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| parallel with a 0.01uF |
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| capacitor. |
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| — If all secondary |
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| devices (and the bus loading) |
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| support |
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| connect PCIXCAP to 3.3V |
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| through an 8.2K Ω resistor |
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| The series resistor on IDSEL should be 200Ω ±5% if it |
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| IDSEL | is exclusively PCIX mode. If it is PCI mode or mixed |
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| PCI/ PCIX mode is intended, 510 ohms is |
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| recommended. |
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Table 21. Miscellaneous Signals
Signals | Recommendations | Reason/Impact |
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RSTIN# | Used for debug purposes. Connect to VCC33 through |
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an 8.2KΩ pullup resistor for normal operation. |
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A_STRAP0, |
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A_STRAP1, | These signals REQUIRE external |
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A_STRAP2, |
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on the board 8.2KΩ unless otherwise stated. |
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A_STRAP6, |
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RESERVED [8:1] |
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Intel® 41110 Serial to Parallel PCI Bridge Design Guide | 57 |