Intel 41110 manual Split Voltage Planes, Decoupling Guidelines, 300, 200

Page 19

Power Plane Layout

Table 2. 41110 Decoupling Guidelines

 

 

41110

C

 

ESR

ESL

# of

 

Voltage Plane

Voltage

Bridge

Package

Location

(uF)

(m)

(nH)

Caps

 

 

Pins

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI/PCI-X

3.3V

VCC33

0.1

0603

50-

1.0-

5

Beneath 41110

Voltage

300

3.0

Bridge BGA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI/PCI-X

3.3V

VCC33

 

 

50-

1.0-

 

As close as design

1.0

0603

2

rules will allow to

Voltage

300

3.0

 

 

 

 

 

41110 Bridge BGA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI/PCI-X

3.3V

VCC33

 

 

50-

1.0-

 

As close as design

10

1206

3

rules will allow to

Voltage

300

3.0

 

 

 

 

 

41110 Bridge BGA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Core Voltage

1.5V

VCC15

0.1

0603

200

2.0

5

Beneath 41110

Bridge BGA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Core Voltage

1.5V

VCC15

 

 

 

 

 

As close as design

1.0

0805

200

2.3

5

rules will allow to

 

 

 

 

 

 

 

 

41110 BridgeBGA

 

 

 

 

 

 

 

 

 

Core Voltage

1.5V

VCC15

 

 

 

 

 

As close as design

10

1206

200

1.9

2

rules will allow to

 

 

 

 

 

 

 

 

41110 Bridge BGA

 

 

 

 

 

 

 

 

 

PCI Express

1.5V

VCCPE

0.1

0603

200

2.0

3

Beneath41110

Voltage

Bridge BGA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Express

1.5V

VCCPE

 

 

 

 

 

As close as design

1

0805

200

2.3

4

rules will allow to

Voltage

 

 

 

 

 

 

 

41110 Bridge BGA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Express

1.5V

VCCPE

 

 

 

 

 

As close as design

10

1206

200

1.9

2

rules will allow to

Voltage

 

 

 

 

 

 

 

41110 Bridge BGA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.2Split Voltage Planes

There are two 1.5V voltage planes that supply power to the 41110:

VCC15:1.5V ±5% (1.5V core voltage)

VCCPE:1.5V ±3% (1.5V PCI Express voltage)

The 41110 Bridge core (VCC15), PCI-Express (VCCPE) voltages should be supplied by two separate voltage regulators or a single regulator. If VCC15 and VCCPE is supplied by a single voltage regulator the power planes should be split as shown in Figure 9.

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

19

Image 19
Contents Design Guide Intel 41110 Serial to Parallel PCI BridgeIntel 41110 Serial to Parallel PCI Bridge Design Guide Contents Tables FiguresContents Date Revision Description March 001 Initial release Revision HistoryTerm Definition About This DocumentTerminology and Definitions Terminology and Definitions Sheet 1Terminology and Definitions Sheet 2 About This DocumentPCI-X Interface Features PCI Express Interface FeaturesIntroduction2 Introduction Power ManagementSMBus for configuration register initialization SMBus InterfaceMicrocontroller Connections to Microcontroller Block DiagramRelated Documents JtagIntel 41110 Serial to Parallel PCI Bridge Applications Block DiagramAdapter Card Block Diagram Package Information Package SpecificationPackage Information Bridge Package Dimensions Side View41110 Decoupling Guidelines Power Plane LayoutPower Plane Layout 300 Split Voltage PlanesDecoupling Guidelines 41110PCI ARST# and PERST# Timing Requirements Reset and Power Timing Considerations5VCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk General Routing Guidelines EMI ConsiderationsTrace Impedance Power Distribution and DecouplingDecoupling Cross Section of Differential Trace Differential ImpedanceAdapter Card Topology Board Layout GuidelinesAdapter Card Stack Up, Microstrip and Stripline Adapter Card Stackup Board Layout GuidelinesINTx Routing Table AINT# Interrupt Pins PCI Express INTx MessagePCI-X Layout Guidelines InterruptsInterrupt Binding for Devices Behind a Bridge PCI ArbitrationInterrupt Routing for Devices Behind a Bridge PCI-X Layout GuidelinesPCI Resistor Compensation PCI General Layout GuidelinesPCI/PCI-X Frequency/Mode Straps PCI-X SignalsPCI Clock Layout Guidelines PCI Pullup Resistors Not RequiredPCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements Summary41110 Layout Analysis PCI-X Topology Layout GuidelinesPCI-X Slot Guidelines Embedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 133 MHzParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHzPCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI 66 MHz Embedded TopologyPCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode TopologyGeneral recommendations PCI Express LayoutAdapter Card Routing Recommendations Sheet 1 PCI-Express Layout GuidelinesAdapter Card Layout Guidelines PCI Express LayoutAdapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations ConfigCircuit Implementations 10.1 41110 Analog Voltage FiltersPCI Express Analog Voltage Filter PCI Analog Voltage FiltersPCI Express Analog Voltage Filter Circuit Bandgap Analog Voltage FilterBandgap Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation PinsSM Bus SMBUs Address ConfigurationBit Value This page intentionally left blank CRB Board Stackup Sheet 1 Layer Type Thickness Copper WeightCustomer Reference Boards Board Stack-upCRB Board Stackup Sheet 2 MaterialImpedance Customer Reference BoardsMechanical Outline Board OutlineThis page intentionally left blank PERCOMP10 Design Guide ChecklistPCI Express Interface Signals Signals Recommendations Reason/ImpactPCI/PCI-X Interface Signals Sheet 1 Design Guide ChecklistMiscellaneous Signals PCI/PCI-X Interface Signals Sheet 2Recommendations Reason/Impact SMBus Interface SignalsBallout Pin Name Usage Reset PinsSignal Recommendations Reason/Impact Power and Ground SignalsJtag Signals This page intentionally left blank