Intel 41110 manual About This Document, Terminology and Definitions Sheet 2

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About This Document

Table 1. Terminology and Definitions (Sheet 2 of 2)

Term

 

 

 

 

 

 

 

Definition

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Layer 1: copper

Printed circuit board.

 

 

 

 

 

 

Example manufacturing process consists of

 

 

 

 

 

 

 

 

 

 

 

 

Prepreg

the following steps:

 

 

 

 

 

 

Layer 2: GND

 

 

 

 

 

 

 

 

 

 

 

 

 

• Consists of alternating layers of core and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Core

 

prepreg stacked

PCB

 

 

 

 

 

Layer 3: VCC15

 

• The finished PCB is heated and cured.

 

 

 

 

 

 

• The via holes are drilled

 

 

 

 

 

 

Prepreg

 

 

 

 

 

 

 

Layer 4: copper

 

• Plating covers holes and outer surfaces

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• Etching removes unwanted copper

 

 

 

Example of a Four-Layer Stack

 

• Board is tinned, coated with solder mask

 

 

 

 

and silk screened

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSTL_2

Series Stub Terminated Logic for 2.5 V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JEDEC

Provides standards for the semiconductor industry.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A network that transmits a coupled signal to another network is aggressor network.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Zo

 

 

 

 

 

 

 

Aggressor

 

 

Zo

 

 

 

Zo

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Zo

 

 

 

 

 

Victim Network

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Aggressor Network

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Victim

A network that receives a coupled cross-talk signal from another network is a victim network.

 

 

 

 

 

 

 

 

 

 

 

 

 

Network

The trace of a PCB that completes an electrical connection between two or more components.

 

 

 

 

 

 

 

 

 

 

 

 

 

Stub

Branch from a trunk terminating at the pad of an agent.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CRB

Customer Reference Board

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Downstream refers either to the relative position of an interconnect/system element (Link/

Downstream

device) as something that is farther from the Root Complex, or to a direction of information

 

flow, i.e., when information is flowing away from the Root Complex.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Upstream

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Local memory

Memory subsystem on the Intel XScale® processor DDR SDRAM or Peripheral Bus Interface

busses.

 

 

 

 

 

 

 

 

 

 

DWORD

32-bit data word.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FC-BGA (flip chip-ball grid array) chip packages are designed with processor core flipped up

Flip Chip

on the back of the chip, facing away from the PCB. This allows more efficient cooling of the

 

package.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mode

Mode Conversions are due to imperfections on the interconnect which transform differential

Conversion

mode voltage to common mode voltage and common mode voltage to differential voltage.

PCI-E

PCI-Express

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Contents Intel 41110 Serial to Parallel PCI Bridge Design GuideIntel 41110 Serial to Parallel PCI Bridge Design Guide Contents Figures TablesContents Revision History Date Revision Description March 001 Initial releaseAbout This Document Terminology and DefinitionsTerminology and Definitions Sheet 1 Term DefinitionAbout This Document Terminology and Definitions Sheet 2Introduction2 PCI Express Interface FeaturesPCI-X Interface Features Power Management SMBus for configuration register initializationSMBus Interface IntroductionMicrocontroller Block Diagram Microcontroller Connections toJtag Related DocumentsBlock Diagram Intel 41110 Serial to Parallel PCI Bridge ApplicationsAdapter Card Block Diagram Package Specification Package InformationBridge Package Dimensions Side View Package InformationPower Plane Layout 41110 Decoupling GuidelinesPower Plane Layout Split Voltage Planes Decoupling Guidelines41110 300PCI VCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations5ARST# and PERST# Timing Requirements Reset and Power Timing Considerations Crosstalk General Routing GuidelinesGeneral Routing Guidelines EMI Considerations General Routing GuidelinesDecoupling Power Distribution and DecouplingTrace Impedance Differential Impedance Cross Section of Differential TraceAdapter Card Stack Up, Microstrip and Stripline Board Layout GuidelinesAdapter Card Topology Board Layout Guidelines Adapter Card StackupAINT# Interrupt Pins PCI Express INTx Message PCI-X Layout GuidelinesInterrupts INTx Routing TablePCI Arbitration Interrupt Routing for Devices Behind a BridgePCI-X Layout Guidelines Interrupt Binding for Devices Behind a BridgePCI General Layout Guidelines PCI Resistor CompensationPCI-X Signals PCI Clock Layout GuidelinesPCI Pullup Resistors Not Required PCI/PCI-X Frequency/Mode StrapsPCI Clock Distribution and Matching Requirements PCI-X Clock Layout Requirements Summary Parameter Routing GuidelinesPCI-X Slot Guidelines PCI-X Topology Layout Guidelines41110 Layout Analysis Parameter Routing Guideline for Lower AD Bus Embedded PCI-X 133 MHzEmbedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 100 MHz Embedded PCI-X 100 MHz Routing RecommendationsPCI-X 66 MHz Embedded Topology PCI-X 66 MHz Embedded Routing RecommendationsPCI 66 MHz Embedded Topology PCI 66 MHz Embedded TablePCI 33 MHz Embedded Mode Topology PCI 33 MHz Embedded Routing RecommendationsPCI Express Layout General recommendationsPCI-Express Layout Guidelines Adapter Card Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Config Circuit Implementations10.1 41110 Analog Voltage Filters Circuit ImplementationsPCI Analog Voltage Filters PCI Express Analog Voltage FilterBandgap Analog Voltage Filter PCI Express Analog Voltage Filter Circuit10.2 41110 Reference and Compensation Pins Bandgap Analog Voltage Filter CircuitBit Value SMBUs Address ConfigurationSM Bus This page intentionally left blank Layer Type Thickness Copper Weight Customer Reference BoardsBoard Stack-up CRB Board Stackup Sheet 1Material ImpedanceCustomer Reference Boards CRB Board Stackup Sheet 2Board Outline Mechanical OutlineThis page intentionally left blank Design Guide Checklist PCI Express Interface SignalsSignals Recommendations Reason/Impact PERCOMP10Design Guide Checklist PCI/PCI-X Interface Signals Sheet 1PCI/PCI-X Interface Signals Sheet 2 Miscellaneous SignalsSMBus Interface Signals Recommendations Reason/ImpactReset Pins Ballout Pin Name UsagePower and Ground Signals Signal Recommendations Reason/ImpactJtag Signals This page intentionally left blank