Intel 41110 manual General Routing Guidelines, Crosstalk

Page 23

General Routing Guidelines

6

This chapter provides some basic routing guidelines for layout and design of a printed circuit board using the 41110. The high-speed clocking required when designing with the 41110 requires special attention to signal integrity. In fact, it is highly recommended that the board design be simulated to determine optimum layout for signal integrity. The information in this chapter provides guidelines to aid the designer with board layout. Several factors influence the signal integrity of a 41110 design. These factors include:

power distribution

minimizing crosstalk

decoupling

layout considerations when routing the PCI Express bus and PCI-X bus interfaces

6.1General Routing Guidelines

This section details general routing guidelines for designing with the 41110. The order in which signals are routed varies from designer to designer. Some designers prefer to route all clock signals first, while others prefer to route all high-speed bus signals first. Either order can be used, provided the guidelines listed here are followed.

6.2Crosstalk

Crosstalk is caused by capacitive and inductive coupling between signals. Crosstalk is composed of both backward and forward crosstalk components. Backward crosstalk creates an induced signal on victim network that propagates in the opposite direction of the aggressor signal. Forward crosstalk creates a signal that propagates in the same direction as the aggressor signal.

Circuit board analysis software is used to analyze your board layout for crosstalk problems. Examples of 2D analysis tools include Parasitic Parameters from ANSOFT* and XFS from Quad Design*. Crosstalk problems occur when circuit etch lines run in parallel. When board analysis software is not available, the layout should be designed to maintain at least the minimum recommended spacing for bus interfaces.

A general guideline to use is, that space distance between adjacent signals be a least 3.3 times the distance from signal trace to the nearest return plane. The coupled noise between adjacent traces decreases by the square of the distance between the adjacent traces.

It is also recommended to specify the height of the above reference plane when laying out traces and provide this parameter to the PCB manufacturer. By moving traces closer to the nearest reference plane, the coupled noise decreases by the square of the distance to the reference plane.

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

23

Image 23
Contents Design Guide Intel 41110 Serial to Parallel PCI BridgeIntel 41110 Serial to Parallel PCI Bridge Design Guide Contents Tables FiguresContents Date Revision Description March 001 Initial release Revision HistoryTerm Definition About This DocumentTerminology and Definitions Terminology and Definitions Sheet 1Terminology and Definitions Sheet 2 About This DocumentIntroduction2 PCI Express Interface FeaturesPCI-X Interface Features Introduction Power ManagementSMBus for configuration register initialization SMBus InterfaceMicrocontroller Connections to Microcontroller Block DiagramRelated Documents JtagIntel 41110 Serial to Parallel PCI Bridge Applications Block DiagramAdapter Card Block Diagram Package Information Package SpecificationPackage Information Bridge Package Dimensions Side View41110 Decoupling Guidelines Power Plane LayoutPower Plane Layout 300 Split Voltage PlanesDecoupling Guidelines 41110PCI VCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations5ARST# and PERST# Timing Requirements Reset and Power Timing Considerations Crosstalk General Routing GuidelinesGeneral Routing Guidelines General Routing Guidelines EMI ConsiderationsDecoupling Power Distribution and DecouplingTrace Impedance Cross Section of Differential Trace Differential ImpedanceAdapter Card Stack Up, Microstrip and Stripline Board Layout GuidelinesAdapter Card Topology Adapter Card Stackup Board Layout GuidelinesINTx Routing Table AINT# Interrupt Pins PCI Express INTx MessagePCI-X Layout Guidelines InterruptsInterrupt Binding for Devices Behind a Bridge PCI ArbitrationInterrupt Routing for Devices Behind a Bridge PCI-X Layout GuidelinesPCI Resistor Compensation PCI General Layout GuidelinesPCI/PCI-X Frequency/Mode Straps PCI-X SignalsPCI Clock Layout Guidelines PCI Pullup Resistors Not RequiredPCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements SummaryPCI-X Slot Guidelines PCI-X Topology Layout Guidelines41110 Layout Analysis Parameter Routing Guideline for Lower AD Bus Embedded PCI-X 133 MHzEmbedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHzPCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI 66 MHz Embedded TopologyPCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode TopologyGeneral recommendations PCI Express LayoutAdapter Card Routing Recommendations Sheet 1 PCI-Express Layout GuidelinesAdapter Card Layout Guidelines PCI Express LayoutAdapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations ConfigCircuit Implementations 10.1 41110 Analog Voltage FiltersPCI Express Analog Voltage Filter PCI Analog Voltage FiltersPCI Express Analog Voltage Filter Circuit Bandgap Analog Voltage FilterBandgap Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation PinsBit Value SMBUs Address ConfigurationSM Bus This page intentionally left blank CRB Board Stackup Sheet 1 Layer Type Thickness Copper WeightCustomer Reference Boards Board Stack-upCRB Board Stackup Sheet 2 MaterialImpedance Customer Reference BoardsMechanical Outline Board OutlineThis page intentionally left blank PERCOMP10 Design Guide ChecklistPCI Express Interface Signals Signals Recommendations Reason/ImpactPCI/PCI-X Interface Signals Sheet 1 Design Guide ChecklistMiscellaneous Signals PCI/PCI-X Interface Signals Sheet 2Recommendations Reason/Impact SMBus Interface SignalsBallout Pin Name Usage Reset PinsSignal Recommendations Reason/Impact Power and Ground SignalsJtag Signals This page intentionally left blank