Intel 41110 manual SMBus Interface Signals, Recommendations Reason/Impact

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Design Guide Checklist

Table 21. Miscellaneous Signals

 

Signals

Recommendations

Reason/Impact

 

 

 

 

 

 

Input pin to configure 41110 to retry configuration

 

 

 

accesses on it's PCI Express interface.

 

 

CFGRETRY

To retry configuration accesses to the 41110, pull high to

 

 

 

3.3V through a 2K resistor.

 

 

 

To allow configuration accesses to the 41110, ground

 

 

 

this pin through a 2K resistor.

 

 

 

 

 

 

A_TEST1,

 

 

 

A_TEST2,

These signals REQUIRE an external pull-up, 8.2Kto

 

 

A_PME#,

 

 

3.3V.

 

 

A_STRAP[3],

 

 

 

 

 

A_STRAP[4],

 

 

 

A_STRAP[5],

 

 

 

 

 

 

 

CMODE

This signal requires an external pull-up, 8.2Kto 3.3V.

In normal operating mode, this

 

 

 

pin must be tied high.

Table 22. SMBus Interface Signals

 

 

 

 

 

 

Signal

Recommendations

Reason/Impact

 

 

 

 

 

SMBCLK

Connect to VCC33 through an 8.2Kpullup resistor.

 

 

 

 

 

 

SMBDAT

Connect to VCC33 through an 8.2Kpullup resistor.

 

 

 

 

 

 

 

SMBus addressing:

 

 

 

Bit 7----------------’1’

 

 

 

Bit 6----------------’1’

 

 

 

Bit 5---------------SMBUS[5]

 

 

 

Bit 4----------------’0’

 

 

SMBUS[5],

Bit 3---------------SMBUS[3]

Sampled on the rising edge of

 

SMBUS[3:1]

Bit 2---------------SMBUS[2]

PERST#.

 

 

 

 

 

Bit 1---------------SMBUS[1]

 

 

 

Use 8.2Kresistors as pullups to VCC33 for a ‘1’ and

 

 

 

as pulldowns to ground for a ‘0’ to set the SMBus

 

 

 

address.

 

 

 

 

 

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Intel® 41110 Serial to Parallel PCI Bridge Design Guide

Image 58
Contents Intel 41110 Serial to Parallel PCI Bridge Design GuideIntel 41110 Serial to Parallel PCI Bridge Design Guide Contents Figures TablesContents Revision History Date Revision Description March 001 Initial releaseTerminology and Definitions Sheet 1 About This DocumentTerminology and Definitions Term DefinitionAbout This Document Terminology and Definitions Sheet 2PCI-X Interface Features PCI Express Interface FeaturesIntroduction2 SMBus Interface Power ManagementSMBus for configuration register initialization IntroductionMicrocontroller Block Diagram Microcontroller Connections toJtag Related DocumentsBlock Diagram Intel 41110 Serial to Parallel PCI Bridge ApplicationsAdapter Card Block Diagram Package Specification Package InformationBridge Package Dimensions Side View Package InformationPower Plane Layout 41110 Decoupling GuidelinesPower Plane Layout 41110 Split Voltage PlanesDecoupling Guidelines 300PCI ARST# and PERST# Timing Requirements Reset and Power Timing Considerations5VCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk EMI Considerations General Routing GuidelinesTrace Impedance Power Distribution and DecouplingDecoupling Differential Impedance Cross Section of Differential TraceAdapter Card Topology Board Layout GuidelinesAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Adapter Card StackupInterrupts AINT# Interrupt Pins PCI Express INTx MessagePCI-X Layout Guidelines INTx Routing TablePCI-X Layout Guidelines PCI ArbitrationInterrupt Routing for Devices Behind a Bridge Interrupt Binding for Devices Behind a BridgePCI General Layout Guidelines PCI Resistor CompensationPCI Pullup Resistors Not Required PCI-X SignalsPCI Clock Layout Guidelines PCI/PCI-X Frequency/Mode StrapsPCI Clock Distribution and Matching Requirements PCI-X Clock Layout Requirements Summary Parameter Routing Guidelines41110 Layout Analysis PCI-X Topology Layout GuidelinesPCI-X Slot Guidelines Embedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 133 MHzParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Embedded PCI-X 100 MHz Routing RecommendationsPCI-X 66 MHz Embedded Topology PCI-X 66 MHz Embedded Routing RecommendationsPCI 66 MHz Embedded Topology PCI 66 MHz Embedded TablePCI 33 MHz Embedded Mode Topology PCI 33 MHz Embedded Routing RecommendationsPCI Express Layout General recommendationsPCI Express Layout PCI-Express Layout GuidelinesAdapter Card Layout Guidelines Adapter Card Routing Recommendations Sheet 1Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank 10.1 41110 Analog Voltage Filters ConfigCircuit Implementations Circuit ImplementationsPCI Analog Voltage Filters PCI Express Analog Voltage FilterBandgap Analog Voltage Filter PCI Express Analog Voltage Filter Circuit10.2 41110 Reference and Compensation Pins Bandgap Analog Voltage Filter CircuitSM Bus SMBUs Address ConfigurationBit Value This page intentionally left blank Board Stack-up Layer Type Thickness Copper WeightCustomer Reference Boards CRB Board Stackup Sheet 1Customer Reference Boards MaterialImpedance CRB Board Stackup Sheet 2Board Outline Mechanical OutlineThis page intentionally left blank Signals Recommendations Reason/Impact Design Guide ChecklistPCI Express Interface Signals PERCOMP10Design Guide Checklist PCI/PCI-X Interface Signals Sheet 1PCI/PCI-X Interface Signals Sheet 2 Miscellaneous SignalsSMBus Interface Signals Recommendations Reason/ImpactReset Pins Ballout Pin Name UsagePower and Ground Signals Signal Recommendations Reason/ImpactJtag Signals This page intentionally left blank