Intel 41110 manual Power and Ground Signals, Signal Recommendations Reason/Impact

Page 60

Design Guide Checklist

Table 24. Power and Ground Signals

	Signal	Recommendations	Reason/Impact

		100Ω ±1% (1/4 W) pulldown resistor to ground.	Analog compensation pin for
	RCOMP		Analog compensation pin for
	RCOMP		PCI. 0.75V nominal.
		The trace impedance of this signal should be < 0.1Ω.	PCI. 0.75V nominal.
		The trace impedance of this signal should be < 0.1Ω.

		Connect to 1.5V power supply.
		Note: Linear voltage regulators are recommended
		when using 1.5 Volt power supplies.
		Decoupling:
	VCC15	5 0.1uF caps beneath package (backside of board)	1.5V ±5% core voltage.
		2 1.0 uF caps as close as design rules permit to
		package
		3 10 uF caps as close as design rules permit to
		package

		Connect to 3.3V power supply.
		Decoupling: TBD
		The platform must insure that the VCC33 voltage rail
		be greater than to (or no less than 0.5V below) VCC15
	VCC33	(absolute voltage value at all times during 41110	3.3V ±5% PCI I/O voltage.
	VCC33	operation, including during system power up, power	3.3V ±5% PCI I/O voltage.
		down or any other time during system operation. This
		can be accomplished by placing a diode (with a voltage
		drop < 0.5V) between VCC15 and VCC33. Anode will
		be connected to VCC15 and cathode will be connected
		to VCC33.

	VCCAPE	Connect to 1.5V power supply.	1.5V ±3% Analog PCI Express
	VCCAPE		voltage.
			voltage.

	VCCAPCI[2:0]	See Figure 22 for circuit.	Analog PCI voltage pins.

		Voltage output of the bandgap filter circuit into 41110,
	VCCBGPE	separated from the rest of the VCC15s. See Figure 24	2.5V ±3% PCI Express voltage.
		for circuit.

		Connect to 1.5V power supply.
		Decoupling:
	VCCPE	• 3 0.1uF caps beneath package (backside of board)	1.5V ±3% PCI Express voltage.
	VCCPE	• 4 1.0 uF caps as close as design rules permit to	1.5V ±3% PCI Express voltage.
		package
		• 2 10 uF caps as close as design rules permit to
		package

	VSS	Connect to ground.	Ground reference for all
	VSS	Connect to ground.	supplies.
			supplies.

	VSSAPE	See Figure 23 for circuit.	Analog ground for PCI Express.

	VSSBGPE	Ground for the bandgap filter circuit, separated from	Ground for analog bandgap
	VSSBGPE	the rest of the VSSs. See Figure 24 for circuit.	voltage.
		the rest of the VSSs. See Figure 24 for circuit.	voltage.

60	Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Contents Intel 41110 Serial to Parallel PCI Bridge Design GuideIntel 41110 Serial to Parallel PCI Bridge Design Guide Contents Figures TablesContents Revision History Date Revision Description March 001 Initial releaseAbout This Document Terminology and DefinitionsTerminology and Definitions Sheet 1 Term DefinitionAbout This Document Terminology and Definitions Sheet 2PCI Express Interface Features PCI-X Interface FeaturesIntroduction2 Power Management SMBus for configuration register initializationSMBus Interface IntroductionMicrocontroller Block Diagram Microcontroller Connections toJtag Related DocumentsBlock Diagram Intel 41110 Serial to Parallel PCI Bridge ApplicationsAdapter Card Block Diagram Package Specification Package InformationBridge Package Dimensions Side View Package InformationPower Plane Layout 41110 Decoupling GuidelinesPower Plane Layout Split Voltage Planes Decoupling Guidelines41110 300PCI Reset and Power Timing Considerations5 ARST# and PERST# Timing RequirementsVCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk EMI Considerations General Routing GuidelinesPower Distribution and Decoupling Trace ImpedanceDecoupling Differential Impedance Cross Section of Differential TraceBoard Layout Guidelines Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Adapter Card StackupAINT# Interrupt Pins PCI Express INTx Message PCI-X Layout GuidelinesInterrupts INTx Routing TablePCI Arbitration Interrupt Routing for Devices Behind a BridgePCI-X Layout Guidelines Interrupt Binding for Devices Behind a BridgePCI General Layout Guidelines PCI Resistor CompensationPCI-X Signals PCI Clock Layout GuidelinesPCI Pullup Resistors Not Required PCI/PCI-X Frequency/Mode StrapsPCI Clock Distribution and Matching Requirements PCI-X Clock Layout Requirements Summary Parameter Routing GuidelinesPCI-X Topology Layout Guidelines 41110 Layout AnalysisPCI-X Slot Guidelines Embedded PCI-X 133 MHz Embedded PCI-X 133 MHz Routing RecommendationsParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Embedded PCI-X 100 MHz Routing RecommendationsPCI-X 66 MHz Embedded Topology PCI-X 66 MHz Embedded Routing RecommendationsPCI 66 MHz Embedded Topology PCI 66 MHz Embedded TablePCI 33 MHz Embedded Mode Topology PCI 33 MHz Embedded Routing RecommendationsPCI Express Layout General recommendationsPCI-Express Layout Guidelines Adapter Card Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Config Circuit Implementations10.1 41110 Analog Voltage Filters Circuit ImplementationsPCI Analog Voltage Filters PCI Express Analog Voltage FilterBandgap Analog Voltage Filter PCI Express Analog Voltage Filter Circuit10.2 41110 Reference and Compensation Pins Bandgap Analog Voltage Filter CircuitSMBUs Address Configuration SM BusBit Value This page intentionally left blank Layer Type Thickness Copper Weight Customer Reference BoardsBoard Stack-up CRB Board Stackup Sheet 1Material ImpedanceCustomer Reference Boards CRB Board Stackup Sheet 2Board Outline Mechanical OutlineThis page intentionally left blank Design Guide Checklist PCI Express Interface SignalsSignals Recommendations Reason/Impact PERCOMP10Design Guide Checklist PCI/PCI-X Interface Signals Sheet 1PCI/PCI-X Interface Signals Sheet 2 Miscellaneous SignalsSMBus Interface Signals Recommendations Reason/ImpactReset Pins Ballout Pin Name UsagePower and Ground Signals Signal Recommendations Reason/ImpactJtag Signals This page intentionally left blank