Intel 41110 manual PCI Clock Distribution and Matching Requirements

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PCI-X Layout Guidelines

distributed to each PCI device. The 41110 provides seven buffered clocks on the PCI bus to connect to multiple PCI-X devices. The Figure 16 shows the use of four PCI “A” clock outputs and length matching requirements. . The recommended clock buffer layout are specified as follows:

•Match each of the used the 41110 output clock lengths A_CLK[6:0] to within 0.1”to help keep the timing within the 0.5 ns maximum budget.

•Keep the distance between the clock lines and other signals “d” at least 25 mils from each other.

•Keep the distance between the clock line and itself “a” at a minimum of 25 mils apart (for serpentine clock layout).

•A_CLKIN gets connected to A_CLKO6 through a 22Ω +/- 1% resistor The 22 +/- 1% Ω resistor is within 500 mils of A_CLKO.

Figure 16. PCI Clock Distribution and Matching Requirements

Serial to

Parallel PCI

Bridge

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Contents Design Guide Intel 41110 Serial to Parallel PCI BridgeIntel 41110 Serial to Parallel PCI Bridge Design Guide Contents Tables FiguresContents Date Revision Description March 001 Initial release Revision HistoryTerminology and Definitions About This DocumentTerminology and Definitions Sheet 1 Term DefinitionTerminology and Definitions Sheet 2 About This DocumentPCI Express Interface Features PCI-X Interface FeaturesIntroduction2 SMBus for configuration register initialization Power ManagementSMBus Interface IntroductionMicrocontroller Connections to Microcontroller Block DiagramRelated Documents JtagIntel 41110 Serial to Parallel PCI Bridge Applications Block DiagramAdapter Card Block Diagram Package Information Package SpecificationPackage Information Bridge Package Dimensions Side View41110 Decoupling Guidelines Power Plane LayoutPower Plane Layout Decoupling Guidelines Split Voltage Planes41110 300PCI Reset and Power Timing Considerations5 ARST# and PERST# Timing RequirementsVCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk General Routing Guidelines EMI ConsiderationsPower Distribution and Decoupling Trace ImpedanceDecoupling Cross Section of Differential Trace Differential ImpedanceBoard Layout Guidelines Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Adapter Card Stackup Board Layout GuidelinesPCI-X Layout Guidelines AINT# Interrupt Pins PCI Express INTx MessageInterrupts INTx Routing TableInterrupt Routing for Devices Behind a Bridge PCI ArbitrationPCI-X Layout Guidelines Interrupt Binding for Devices Behind a BridgePCI Resistor Compensation PCI General Layout GuidelinesPCI Clock Layout Guidelines PCI-X SignalsPCI Pullup Resistors Not Required PCI/PCI-X Frequency/Mode StrapsPCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements SummaryPCI-X Topology Layout Guidelines 41110 Layout AnalysisPCI-X Slot Guidelines Embedded PCI-X 133 MHz Embedded PCI-X 133 MHz Routing RecommendationsParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHzPCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI 66 MHz Embedded TopologyPCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode TopologyGeneral recommendations PCI Express LayoutAdapter Card Layout Guidelines PCI-Express Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations Config10.1 41110 Analog Voltage Filters Circuit ImplementationsPCI Express Analog Voltage Filter PCI Analog Voltage FiltersPCI Express Analog Voltage Filter Circuit Bandgap Analog Voltage FilterBandgap Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation PinsSMBUs Address Configuration SM BusBit Value This page intentionally left blank Customer Reference Boards Layer Type Thickness Copper WeightBoard Stack-up CRB Board Stackup Sheet 1Impedance MaterialCustomer Reference Boards CRB Board Stackup Sheet 2Mechanical Outline Board OutlineThis page intentionally left blank PCI Express Interface Signals Design Guide ChecklistSignals Recommendations Reason/Impact PERCOMP10PCI/PCI-X Interface Signals Sheet 1 Design Guide ChecklistMiscellaneous Signals PCI/PCI-X Interface Signals Sheet 2Recommendations Reason/Impact SMBus Interface SignalsBallout Pin Name Usage Reset PinsSignal Recommendations Reason/Impact Power and Ground SignalsJtag Signals This page intentionally left blank