Intel 41110 manual PCI-X Layout Guidelines, Interrupts, INTx Routing Table

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PCI-X Layout Guidelines

8

This chapter describes several factors to be considered with a 41110 PCI/PCI-X design. These include the PCI IDSEL, PCI RCOMP, PCI Interrupts and PCI arbitration.

8.1Interrupts

PCI Express provides interrupt messages that emulate the legacy wired mechanism. This allows IO devices to signal PCI-style interrupts using a pair of ASSERT and DEASSERT messages This message pairing preserves the level-sensitive semantics of the PCI interrupts on PCI Express.

The 41110 uses four interrupts - A_INTA:A_INTD on bus A segment corresponding to the four interrupts defined in the PCI specification. The 41110 routes its PCI interrupt pins and the internal interrupts to PCI Express INTx interrupts according to Table 4.

Table 4. INTx Routing Table

A_INT# Interrupt Pins	PCI Express INTx Message

A_INTA	INTA

A_INTB	INTB

A_INTC	INTC

A_INTD	INTD

The 41110 will use its primary bus number and device number in the Requester ID field for the PCI Express INTx messages. As stated in the PCI Express specification, the function number is reserved for interrupt messages and will always be 0.

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Contents Design Guide Intel 41110 Serial to Parallel PCI BridgeIntel 41110 Serial to Parallel PCI Bridge Design Guide Contents Tables FiguresContents Date Revision Description March 001 Initial release Revision HistoryTerminology and Definitions About This DocumentTerminology and Definitions Sheet 1 Term DefinitionTerminology and Definitions Sheet 2 About This DocumentIntroduction2 PCI Express Interface FeaturesPCI-X Interface Features SMBus for configuration register initialization Power ManagementSMBus Interface IntroductionMicrocontroller Connections to Microcontroller Block DiagramRelated Documents JtagIntel 41110 Serial to Parallel PCI Bridge Applications Block DiagramAdapter Card Block Diagram Package Information Package SpecificationPackage Information Bridge Package Dimensions Side View41110 Decoupling Guidelines Power Plane LayoutPower Plane Layout Decoupling Guidelines Split Voltage Planes41110 300PCI VCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations5ARST# and PERST# Timing Requirements Reset and Power Timing Considerations Crosstalk General Routing GuidelinesGeneral Routing Guidelines General Routing Guidelines EMI ConsiderationsDecoupling Power Distribution and DecouplingTrace Impedance Cross Section of Differential Trace Differential ImpedanceAdapter Card Stack Up, Microstrip and Stripline Board Layout GuidelinesAdapter Card Topology Adapter Card Stackup Board Layout GuidelinesPCI-X Layout Guidelines AINT# Interrupt Pins PCI Express INTx MessageInterrupts INTx Routing TableInterrupt Routing for Devices Behind a Bridge PCI ArbitrationPCI-X Layout Guidelines Interrupt Binding for Devices Behind a BridgePCI Resistor Compensation PCI General Layout GuidelinesPCI Clock Layout Guidelines PCI-X SignalsPCI Pullup Resistors Not Required PCI/PCI-X Frequency/Mode StrapsPCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements SummaryPCI-X Slot Guidelines PCI-X Topology Layout Guidelines41110 Layout Analysis Parameter Routing Guideline for Lower AD Bus Embedded PCI-X 133 MHzEmbedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHzPCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI 66 MHz Embedded TopologyPCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode TopologyGeneral recommendations PCI Express LayoutAdapter Card Layout Guidelines PCI-Express Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations Config10.1 41110 Analog Voltage Filters Circuit ImplementationsPCI Express Analog Voltage Filter PCI Analog Voltage FiltersPCI Express Analog Voltage Filter Circuit Bandgap Analog Voltage FilterBandgap Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation PinsBit Value SMBUs Address ConfigurationSM Bus This page intentionally left blank Customer Reference Boards Layer Type Thickness Copper WeightBoard Stack-up CRB Board Stackup Sheet 1Impedance MaterialCustomer Reference Boards CRB Board Stackup Sheet 2Mechanical Outline Board OutlineThis page intentionally left blank PCI Express Interface Signals Design Guide ChecklistSignals Recommendations Reason/Impact PERCOMP10PCI/PCI-X Interface Signals Sheet 1 Design Guide ChecklistMiscellaneous Signals PCI/PCI-X Interface Signals Sheet 2Recommendations Reason/Impact SMBus Interface SignalsBallout Pin Name Usage Reset PinsSignal Recommendations Reason/Impact Power and Ground SignalsJtag Signals This page intentionally left blank