Intel 41110 PCI-Express Layout Guidelines, Adapter Card Layout Guidelines, PCI Express Layout

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PCI Express Layout

9.2PCI-Express Layout Guidelines

The layout guidelines for PCI-Express were developed for an adapter card topologies. The models and assumptions used in development of these guidelines were as follows:

•Add-In Card Stackup: 60 Ω single-ended impedance

•Target Differential Impedance: 100 Ω +/- 20%.

•Driver Model: 41110 PCI-E IBIS

•Receiver Model: 41110 PCI-E IBIS. Specification model did not meet specifications

•Driver Package Model: Preliminary 41110 model.

•No receiver package model used since specification eye is at package pin.

•Assumed that traces in a lane could be routed totally on microstrip, totally on stripline, or a mixture of microstrip and stripline.

•AC coupling capacitors were modeled as a parasitic resistor and inductor in series.

•Add-in card was modeled as micro-strip routes only.

•No vias were modeled at this time.

•Only the receiver eye was evaluated. The next revision will evaluate the eye at the transmitter and connector as well as the receiver.

9.3Adapter Card Layout Guidelines

Table 15.	Adapter Card Routing Recommendations (Sheet 1 of 2)

	Parameter	Routing Guidelines

	Reference Plane	Route over an unbroken ground plane

	Target Single Ended	60 Ω nominal
	Impedance	60 Ω nominal
	Impedance

	Target Differential	100 Ω +/- 20% Differential Impedance
	Impedance	100 Ω +/- 20% Differential Impedance
	Impedance
	Microstrip and Stripline Trace	4 mils
	Width
		Intrapair: 10 mils center-to-center
		Interpair: 30 mils center-to-center
	Microstrip Trace Spacing	22 mils. center to center (pair to pair).
	Microstrip Trace Spacing	Transmit and Receive pairs should be interleaved. If no interleaving, then inter

		pair spacing should be increased to 50 mils (c2c). Center to center of inter pair is
		defined as center of Positive of one pair to Center of Negative of the next or vice
		versa

	Group Spacing	Spacing from other groups: 25 mils minimum, center to center

	Transmit Trace Length
	(41110 signal pin to AC	0.25”- 5.0” max
	coupling capacitor.)

	Transmit Trace Length (AC
	coupling capacitor to card	1.00”- 4.5” max
	edge finger.)

42	Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Contents Intel 41110 Serial to Parallel PCI Bridge Design GuideIntel 41110 Serial to Parallel PCI Bridge Design Guide Contents Figures TablesContents Revision History Date Revision Description March 001 Initial releaseTerminology and Definitions Sheet 1 About This DocumentTerminology and Definitions Term DefinitionAbout This Document Terminology and Definitions Sheet 2PCI Express Interface Features PCI-X Interface FeaturesIntroduction2 SMBus Interface Power ManagementSMBus for configuration register initialization IntroductionMicrocontroller Block Diagram Microcontroller Connections toJtag Related DocumentsBlock Diagram Intel 41110 Serial to Parallel PCI Bridge ApplicationsAdapter Card Block Diagram Package Specification Package InformationBridge Package Dimensions Side View Package InformationPower Plane Layout 41110 Decoupling GuidelinesPower Plane Layout 41110 Split Voltage PlanesDecoupling Guidelines 300PCI Reset and Power Timing Considerations5 ARST# and PERST# Timing RequirementsVCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk EMI Considerations General Routing GuidelinesPower Distribution and Decoupling Trace ImpedanceDecoupling Differential Impedance Cross Section of Differential TraceBoard Layout Guidelines Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Adapter Card StackupInterrupts AINT# Interrupt Pins PCI Express INTx MessagePCI-X Layout Guidelines INTx Routing TablePCI-X Layout Guidelines PCI ArbitrationInterrupt Routing for Devices Behind a Bridge Interrupt Binding for Devices Behind a BridgePCI General Layout Guidelines PCI Resistor CompensationPCI Pullup Resistors Not Required PCI-X SignalsPCI Clock Layout Guidelines PCI/PCI-X Frequency/Mode StrapsPCI Clock Distribution and Matching Requirements PCI-X Clock Layout Requirements Summary Parameter Routing GuidelinesPCI-X Topology Layout Guidelines 41110 Layout AnalysisPCI-X Slot Guidelines Embedded PCI-X 133 MHz Embedded PCI-X 133 MHz Routing RecommendationsParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Embedded PCI-X 100 MHz Routing RecommendationsPCI-X 66 MHz Embedded Topology PCI-X 66 MHz Embedded Routing RecommendationsPCI 66 MHz Embedded Topology PCI 66 MHz Embedded TablePCI 33 MHz Embedded Mode Topology PCI 33 MHz Embedded Routing RecommendationsPCI Express Layout General recommendationsPCI Express Layout PCI-Express Layout GuidelinesAdapter Card Layout Guidelines Adapter Card Routing Recommendations Sheet 1Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank 10.1 41110 Analog Voltage Filters ConfigCircuit Implementations Circuit ImplementationsPCI Analog Voltage Filters PCI Express Analog Voltage FilterBandgap Analog Voltage Filter PCI Express Analog Voltage Filter Circuit10.2 41110 Reference and Compensation Pins Bandgap Analog Voltage Filter CircuitSMBUs Address Configuration SM BusBit Value This page intentionally left blank Board Stack-up Layer Type Thickness Copper WeightCustomer Reference Boards CRB Board Stackup Sheet 1Customer Reference Boards MaterialImpedance CRB Board Stackup Sheet 2Board Outline Mechanical OutlineThis page intentionally left blank Signals Recommendations Reason/Impact Design Guide ChecklistPCI Express Interface Signals PERCOMP10Design Guide Checklist PCI/PCI-X Interface Signals Sheet 1PCI/PCI-X Interface Signals Sheet 2 Miscellaneous SignalsSMBus Interface Signals Recommendations Reason/ImpactReset Pins Ballout Pin Name UsagePower and Ground Signals Signal Recommendations Reason/ImpactJtag Signals This page intentionally left blank