Intel 41110 manual Embedded PCI-X 100 MHz Routing Recommendations

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PCI-X Layout Guidelines

8.6.2Embedded PCI-X 100 MHz

This section lists the embedded routing recommendations for PCI-X 100 MHz. Figure 18 shows the block diagram of this topology and Table 11 describes the routing recommendations.

Figure 18. Embedded PCI-X 100 MHz Topology

TL_EM1 EM1

TL1

TL_EM3 EM3

TL_EM2 EM2

B2720 -01

Table 11.

Embedded PCI-X 100 MHz Routing Recommendations

 

 

 

 

Parameter

Routing Guideline for Lower AD Bus

 

 

 

 

Reference Plane

Route over an unbroken ground plane

 

 

 

 

Board Impedance

60 +/- 15%

 

 

 

 

Stripline Trace Spacing

12 mils from edge to edge

 

 

 

 

Microstrip Trace Spacing

18 mils, from edge to edge

 

 

 

 

Break Out

5 mils on 5 mils spacing. Maximum length of breakout region can be 500 mils

 

 

 

 

Group Spacing

Spacing from other groups: 25 mils min, edge to edge

 

 

 

 

Trace Length 1 (TL1): From

 

 

41110 signal Ball to first

0.5” min - 3.0” max

 

junction

 

 

 

 

 

Trace Length: TL_EM1: from

 

 

41110 signal ball to the first

2.5” min - 3.5” max

 

embedded device

 

 

Trace Length TL_EM2 -

 

 

TL_EM3: from junction to the

1.5” min - 3.5” max

 

embedded device

 

 

 

 

 

Length Matching

Clocks coming form the clock driver must be on the same layer and length

 

Requirements:

matched to within 25 mils.

 

 

 

 

Number of vias

4 vias max per path

 

 

 

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Contents Design Guide Intel 41110 Serial to Parallel PCI BridgeIntel 41110 Serial to Parallel PCI Bridge Design Guide Contents Tables FiguresContents Date Revision Description March 001 Initial release Revision HistoryTerminology and Definitions About This DocumentTerminology and Definitions Sheet 1 Term DefinitionTerminology and Definitions Sheet 2 About This DocumentPCI-X Interface Features PCI Express Interface FeaturesIntroduction2 SMBus for configuration register initialization Power ManagementSMBus Interface IntroductionMicrocontroller Connections to Microcontroller Block DiagramRelated Documents JtagIntel 41110 Serial to Parallel PCI Bridge Applications Block DiagramAdapter Card Block Diagram Package Information Package SpecificationPackage Information Bridge Package Dimensions Side View41110 Decoupling Guidelines Power Plane LayoutPower Plane Layout Decoupling Guidelines Split Voltage Planes41110 300PCI ARST# and PERST# Timing Requirements Reset and Power Timing Considerations5VCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk General Routing Guidelines EMI ConsiderationsTrace Impedance Power Distribution and DecouplingDecoupling Cross Section of Differential Trace Differential ImpedanceAdapter Card Topology Board Layout GuidelinesAdapter Card Stack Up, Microstrip and Stripline Adapter Card Stackup Board Layout GuidelinesPCI-X Layout Guidelines AINT# Interrupt Pins PCI Express INTx MessageInterrupts INTx Routing TableInterrupt Routing for Devices Behind a Bridge PCI ArbitrationPCI-X Layout Guidelines Interrupt Binding for Devices Behind a BridgePCI Resistor Compensation PCI General Layout GuidelinesPCI Clock Layout Guidelines PCI-X SignalsPCI Pullup Resistors Not Required PCI/PCI-X Frequency/Mode StrapsPCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements Summary41110 Layout Analysis PCI-X Topology Layout GuidelinesPCI-X Slot Guidelines Embedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 133 MHzParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHzPCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI 66 MHz Embedded TopologyPCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode TopologyGeneral recommendations PCI Express LayoutAdapter Card Layout Guidelines PCI-Express Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations Config10.1 41110 Analog Voltage Filters Circuit ImplementationsPCI Express Analog Voltage Filter PCI Analog Voltage FiltersPCI Express Analog Voltage Filter Circuit Bandgap Analog Voltage FilterBandgap Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation PinsSM Bus SMBUs Address ConfigurationBit Value This page intentionally left blank Customer Reference Boards Layer Type Thickness Copper WeightBoard Stack-up CRB Board Stackup Sheet 1Impedance MaterialCustomer Reference Boards CRB Board Stackup Sheet 2Mechanical Outline Board OutlineThis page intentionally left blank PCI Express Interface Signals Design Guide ChecklistSignals Recommendations Reason/Impact PERCOMP10PCI/PCI-X Interface Signals Sheet 1 Design Guide ChecklistMiscellaneous Signals PCI/PCI-X Interface Signals Sheet 2Recommendations Reason/Impact SMBus Interface SignalsBallout Pin Name Usage Reset PinsSignal Recommendations Reason/Impact Power and Ground SignalsJtag Signals This page intentionally left blank