Intel 41110 manual Reset Pins, Ballout Pin Name Usage

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Design Guide Checklist

Table 23. Reset Pins

Ballout

Pin Name

Usage

 

 

 

E6

STRAP_V_1

Pull up to VCC33

 

 

 

B5

STRAP_V_2

Pull up to VCC33

 

 

 

B3

STRAP_V_3

Pull up to VCC33

 

 

 

A3

STRAP_V_4

Pull up to VCC33

 

 

 

B4

STRAP_V_5

Pull up to VCC33

 

 

 

D4

STRAP_V_6

Pull up to VCC33

 

 

 

F5

STRAP_V_7

Pull up to VCC33

 

 

 

P2

STRAP_V_8

Pull up to VCC33

 

 

 

C3

STRAP_V_9

Pull up to VCC33

 

 

 

D1

STRAP_V_10

Pull up to VCC33

 

 

 

U1

STRAP_V_11

Pull up to VCC33

 

 

 

D7

STRAP_V_12

Pull up to VCC33

 

 

 

U10

STRAP_V_13

Pull up to VCC33

 

 

 

R5

STRAP_V_14

Pull up to VCC33

 

 

 

A19

STRAP_V_15

Pull down to GND

 

 

 

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Contents Design Guide Intel 41110 Serial to Parallel PCI BridgeIntel 41110 Serial to Parallel PCI Bridge Design Guide Contents Tables FiguresContents Date Revision Description March 001 Initial release Revision HistoryTerm Definition About This DocumentTerminology and Definitions Terminology and Definitions Sheet 1Terminology and Definitions Sheet 2 About This DocumentIntroduction2 PCI Express Interface FeaturesPCI-X Interface Features Introduction Power ManagementSMBus for configuration register initialization SMBus InterfaceMicrocontroller Connections to Microcontroller Block DiagramRelated Documents JtagIntel 41110 Serial to Parallel PCI Bridge Applications Block DiagramAdapter Card Block Diagram Package Information Package SpecificationPackage Information Bridge Package Dimensions Side View41110 Decoupling Guidelines Power Plane LayoutPower Plane Layout 300 Split Voltage PlanesDecoupling Guidelines 41110PCI VCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations5ARST# and PERST# Timing Requirements Reset and Power Timing Considerations Crosstalk General Routing GuidelinesGeneral Routing Guidelines General Routing Guidelines EMI ConsiderationsDecoupling Power Distribution and DecouplingTrace Impedance Cross Section of Differential Trace Differential ImpedanceAdapter Card Stack Up, Microstrip and Stripline Board Layout GuidelinesAdapter Card Topology Adapter Card Stackup Board Layout GuidelinesINTx Routing Table AINT# Interrupt Pins PCI Express INTx MessagePCI-X Layout Guidelines InterruptsInterrupt Binding for Devices Behind a Bridge PCI ArbitrationInterrupt Routing for Devices Behind a Bridge PCI-X Layout GuidelinesPCI Resistor Compensation PCI General Layout GuidelinesPCI/PCI-X Frequency/Mode Straps PCI-X SignalsPCI Clock Layout Guidelines PCI Pullup Resistors Not RequiredPCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements SummaryPCI-X Slot Guidelines PCI-X Topology Layout Guidelines41110 Layout Analysis Parameter Routing Guideline for Lower AD Bus Embedded PCI-X 133 MHzEmbedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHzPCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI 66 MHz Embedded TopologyPCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode TopologyGeneral recommendations PCI Express LayoutAdapter Card Routing Recommendations Sheet 1 PCI-Express Layout GuidelinesAdapter Card Layout Guidelines PCI Express LayoutAdapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations ConfigCircuit Implementations 10.1 41110 Analog Voltage FiltersPCI Express Analog Voltage Filter PCI Analog Voltage FiltersPCI Express Analog Voltage Filter Circuit Bandgap Analog Voltage FilterBandgap Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation PinsBit Value SMBUs Address ConfigurationSM Bus This page intentionally left blank CRB Board Stackup Sheet 1 Layer Type Thickness Copper WeightCustomer Reference Boards Board Stack-upCRB Board Stackup Sheet 2 MaterialImpedance Customer Reference BoardsMechanical Outline Board OutlineThis page intentionally left blank PERCOMP10 Design Guide ChecklistPCI Express Interface Signals Signals Recommendations Reason/ImpactPCI/PCI-X Interface Signals Sheet 1 Design Guide ChecklistMiscellaneous Signals PCI/PCI-X Interface Signals Sheet 2Recommendations Reason/Impact SMBus Interface SignalsBallout Pin Name Usage Reset PinsSignal Recommendations Reason/Impact Power and Ground SignalsJtag Signals This page intentionally left blank