Texas Instruments TMS320C6455 manual Clock Control, Memory Map, Signal Descriptions

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Peripheral Architecture

2Peripheral Architecture

The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters.

The following sections describe the architecture of the DDR2 memory controller as well as how to interface and configure it to perform read and write operations to DDR2 SDRAM devices. Also, Section 3 provides a detailed example of interfacing the DDR2 memory controller to a common DDR2 SDRAM device.

2.1Clock Control

The DDR2 memory controller is clocked directly from the output of the second phase-locked loop (PLL2) of C6455/C6454 devices. The PLL2 multiplies its input clock by 20. This clock is divided by 2 to generate DDR2CLKOUT. The frequency of DDR2CLKOUT can be determined by using the following formula:

DDR2CLKOUT frequency = (PLL2 input clock frequency × 20)/2 = PLL2 input clock frequency×10

The second output clock of the DDR2 memory controller, DDR2CLKOUT, is the inverse of DDR2CLKOUT. For more information on the PLL2, see the device-specific data manual.

2.2Memory Map

For information describing the device memory map, see the device-specific data manual.

2.3Signal Descriptions

The DDR2 memory controller signals are shown in Figure 2 and described in Table 1. The following features are included:

•The maximum width for the data bus (DED[31:0]) is 32-bits.

•The address bus (DEA[13:0]) is 14-bits wide with an additional 3 bank address pins (DBA[2:0]).

•Two differential output clocks (DDR2CLKOUT and DDR2CLKOUT) driven by internal clock sources.

•Command signals: Row and column address strobe (DSDRAS and DSDCAS), write enable strobe (DSDWE), data strobe (DSDDQS[3:0] and DSDDQS[3:0]), and data mask (DSDDQM[3:0]).

•One chip select signal (DCE0).

•One clock enable signal (DSDCKE).

•Two on-die termination output signals (DEODT[1:0]). (These pins are reserved for future use.)

SPRU970G – December 2005 – Revised June 2011	C6455/C6454 DDR2 Memory Controller	11
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control Pin Description DDR2 Memory Controller Signal DescriptionsProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsRefresh Command Refresh ModeActivation Actv Actv CommandDeactivation Dcab and Deac Dcab CommandDeac Command DDR2 Read Command Read CommandAddress Type Generated by DDR2 Write WRT CommandMemory Width, Byte Alignment, and Endianness Addressable Memory RangesIbank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit DescriptionLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency LevelsDDR2 Memory Controller Reset Effect Initiated by Self-Refresh ModeReset Considerations Device and DDR2 Memory Controller Reset RelationshipMode Register Field 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 ConfigurationEdma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Field Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register SdrfcSDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet ParameterRegister Description DDR2 Memory Controller RegistersOffset Bit Field Value Description Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions Ifrdy DDR2 Memory Controller Status Register DmcstatSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcTras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWRUsing this formula Txsrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt TxsnrPrioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History TI E2E Community Home Products ApplicationsDSP Rfid