Texas Instruments TMS320C6455 manual DDR2 Memory Refresh Specification, Sdrfc Configuration

Page 36

Using the DDR2 Memory Controller

www.ti.com

Table 12 displays the DDR2-533 refresh rate specification.

Table 12. DDR2 Memory Refresh Specification

Symbol	Description	Value
tREF	Average Periodic Refresh Interval	7.8 μs

Therefore, the value for the REFRESH-RATE can be calculated as follows:

REFRESH_RATE = 250 MHz × 7.8 μs = 1950 = 79Eh

Table 13 shows the resulting SDRFC configuration.

		Table 13. SDRFC Configuration

Field	Value		Function Selection

SR	0		DDR2 memory controller is not in self-refresh mode.
REFRESH_RATE	79Eh		Set to 79Eh DDR2 clock cycles to meet the DDR2 memory refresh rate
			requirement.

3.2.3Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2)

The SDRAM timing 1 register (SDTIM1) and SDRAM timing 2 register (SDTIM2) configure the DDR2 memory controller to meet the data sheet timing parameters of the attached DDR2 device. Each field in SDTIM1 and SDTIM2 corresponds to a timing parameter in the DDR2 data sheet specification. Table 14 and Table 15 display the register field name and corresponding DDR2 data sheet parameter name along with the data sheet value. These tables also provide a formula to calculate the register field value and displays the resulting calculation. Each of the equations include a minus 1 because the register fields are defined in terms of DDR2 clock cycles minus 1. See Section 4.5 and Section 4.6 for more information.

Table 14. SDTIM1 Configuration

	DDR2 SDRAM
Register Field	Data Sheet		Data Sheet	Formula (Register Field Must	Field
Name	Parameter Name	Description	Value (ns)	Be ≥)	Value
T_RFC	tRFC	Refresh cycle time	127.5	(tRFC × fDDR2_CLK) - 1	31
T_RP	tRP	Precharge command to	15	(tRP × fDDR2_CLK) - 1	3
		refresh or activate
		command
T_RCD	tRCD	Activate command to	15	(tRCD × fDDR2_CLK) - 1	3
		read/write command
T_WR	tWR	Write recovery time	15	(tWR × fDDR2_CLK) - 1	3
T_RAS	tRAS	Active to precharge	45	(tRAC × fDDR2_CLK) - 1	11
		command
T_RC	tRC	Activate to Activate	60	(tRC × fDDR2_CLK) - 1	14
		command in the same
		bank
T_RRD	tRRD	Activate to Activate	10	( (4trrd + 2tck) / (4*tck) ) - 1	2
		command in a different
		bank
T_WTR	tWTR	Write to read command	7.5	(tWTR × fDDR2_CLK) - 1	1
		delay

36 C6455/C6454 DDR2 Memory Controller	SPRU970G – December 2005 – Revised June 2011
	Submit Documentation Feedback

Copyright © 2005–2011, Texas Instruments Incorporated

Image 36

Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map DDR2 Memory Controller Signal Descriptions Pin DescriptionDDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol DescriptionsMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandRefresh Mode Refresh CommandActv Command Activation ActvDcab Command Deactivation Dcab and DeacDeac Command Read Command DDR2 Read CommandWrite WRT Command Memory Width, Byte Alignment, and EndiannessAddressable Memory Ranges Address Type Generated by DDR2Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Scheduling Possible Race ConditionRefresh Urgency Levels Urgency Level DescriptionSelf-Refresh Mode Reset ConsiderationsDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated by11.1 DDR2 Sdram Device Mode Register Configuration Values DDR2 Sdram Mode Register ConfigurationDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field11.2 DDR2 Sdram Initialization After Reset 11.3 DDR2 Sdram Initialization After Register ConfigurationInterrupt Support Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Configuration Register Sdcfg Sdcfg ConfigurationProgramming the Sdram Refresh Control Register Sdrfc FieldDDR2 Memory Refresh Specification Sdrfc ConfigurationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationSDTIM2 Configuration Dmcctl ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionDDR2 Memory Controller Registers OffsetRegister Description Module ID and Revision Register Midr Module ID and Revision Register Midr Field DescriptionsBit Field Value Description DDR2 Memory Controller Status Register Dmcstat IfrdySdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsSdram Timing 1 Register SDTIM1 Sdram Timing 1 Register SDTIM1 Field DescriptionsTrfc TRP Trcd TWR Tras TRC TrrdUsing this formula Sdram Timing 2 Register SDTIM2 Sdram Timing 2 Register SDTIM2 Field DescriptionsTodt Txsnr Txsrd Trtp TckeBurst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History Products Applications DSPRfid TI E2E Community Home