Texas Instruments TMS320C6455 manual List of Tables

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	List of Tables
1	DDR2 Memory Controller Signal Descriptions	12
2	DDR2 SDRAM Commands	13
3	Truth Table for DDR2 SDRAM Commands	13
4	Addressable Memory Ranges	20
5	Bank Configuration Register Fields for Address Mapping	21
6	DDR2 Memory Controller FIFO Description	24
7	Refresh Urgency Levels	27
8	Device and DDR2 Memory Controller Reset Relationship	28
9	DDR2 SDRAM Mode Register Configuration	29
10	DDR2 SDRAM Extended Mode Register 1 Configuration	29
11	SDCFG Configuration	35
12	DDR2 Memory Refresh Specification	36
13	SDRFC Configuration	36
14	SDTIM1 Configuration	36
15	SDTIM2 Configuration	37
16	DMCCTL Configuration	37
17	DDR2 Memory Controller Registers	38
18	Module ID and Revision Register (MIDR) Field Descriptions	39
19	DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions	40
20	SDRAM Configuration Register (SDCFG) Field Descriptions	41
21	SDRAM Refresh Control Register (SDRFC) Field Descriptions	43
22	SDRAM Timing 1 Register (SDTIM1) Field Descriptions	44
23	SDRAM Timing 2 Register (SDTIM2) Field Descriptions	46
24	Burst Priority Register (BPRIO) Field Descriptions	47
25	DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions	48

SPRU970G – December 2005 – Revised June 2011	List of Tables	5
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control Pin Description DDR2 Memory Controller Signal DescriptionsTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsRefresh Command Refresh ModeActivation Actv Actv CommandDeactivation Dcab and Deac Dcab CommandDeac Command DDR2 Read Command Read CommandMemory Width, Byte Alignment, and Endianness Write WRT CommandAddressable Memory Ranges Address Type Generated by DDR2Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level DescriptionReset Considerations Self-Refresh ModeDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated byDDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc FieldSdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationDmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionRegister Description DDR2 Memory Controller RegistersOffset Bit Field Value Description Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions Ifrdy DDR2 Memory Controller Status Register DmcstatSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcSdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC TrrdUsing this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Txsnr Txsrd Trtp TckePrioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History DSP Products ApplicationsRfid TI E2E Community Home