Texas Instruments TMS320C6455 manual SDTIM2 Configuration, Dmcctl Configuration, Name Description

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www.ti.comUsing the DDR2 Memory Controller

Table 15. SDTIM2 Configuration

	DDR2 SDRAM Data
Register Field	Sheet Parameter		Data Sheet	Formula (Register	Field
Name	Name	Description	Value	Field Must Be ≥)	Value
T_ODT	tAOND	tAOND specifies the ODT turn-on	2 (tCK cycles)	tAOND	2
		delay
T_XSNR	tXSNR	Exit self refresh to a non-read	137.5 ns	(tXSNR × fDDR2_CLK) - 1	34
		command
T_XSRD	tXSRD	Exit self refresh to a read	200 (tCK cycles)	(tXSRD) - 1	199
		command
T_RTP	tRTP	Read to precharge command	7.5 ns	(tRTP × fDDR2_CLK) - 1	1
		delay
T_CKE	tCKE	CKE minimum pulse width	3 (tCK cycles)	(tCKE) - 1	2

3.2.4Configuring the DDR2 Memory Controller Control Register (DMCCTL)

The DDR2 memory controller control register (DMCCTL) contains a read latency (RL) field that helps the DDR2 memory controller determine when to sample read data. The RL field should be programmed to a value equal to CAS latency + 1. For example, if a CAS latency of 4 is used, then RL should be programmed to 5.

Table 16. DMCCTL Configuration

		Register
Register Field Name	Description	Value

IFRESET	Programmed to be out of reset.	0
RL	Read latency is equal to CAS latency + 1.	5

SPRU970G – December 2005 – Revised June 2011	C6455/C6454 DDR2 Memory Controller	37
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map Pin Description DDR2 Memory Controller Signal DescriptionsTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsRefresh Command Refresh ModeActivation Actv Actv CommandDeactivation Dcab and Deac Dcab CommandDeac Command DDR2 Read Command Read CommandMemory Width, Byte Alignment, and Endianness Write WRT CommandAddressable Memory Ranges Address Type Generated by DDR2Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level DescriptionReset Considerations Self-Refresh ModeDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated byDDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc FieldSdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationDmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionOffset DDR2 Memory Controller RegistersRegister Description Module ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrBit Field Value Description Ifrdy DDR2 Memory Controller Status Register DmcstatSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcSdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC TrrdUsing this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Txsnr Txsrd Trtp TckeBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History DSP Products ApplicationsRfid TI E2E Community Home