Texas Instruments TMS320C6455 Sdram Timing 1 Register SDTIM1, Trfc TRP Trcd TWR, Tras TRC Trrd

Page 44

DDR2 Memory Controller Registers

www.ti.com

4.5SDRAM Timing 1 Register (SDTIM1)

The SDRAM timing 1 register (SDTIM1) configures the DDR2 memory controller to meet many of the AC timing specification of the DDR2 memory. Note that DDR2CLKOUT is equal to the period of the DDR2CLKOUT signal. For information on the appropriate values to program each field, see the DDR2 memory section of the device-specific data manual. The bit fields in the SDTIM1 register are only writeable when the TIMUNLOCK bit of the SDRAM Configuration register (SDCFG) is unlocked. The SDTIM1 is shown in Figure 23 and described in Table 22.

Figure 23. SDRAM Timing 1 Register (SDTIM1)

31

 

25

24

22

21

19

18

 

16

T_RFC

 

 

 

T_RP

 

T_RCD

 

 

T_WR

 

R/W-0x3F

 

 

 

R/W-0x7

 

R/W-0x7

 

 

R/W-0x7

 

15

11

10

 

 

6

5

3

2

1

0

 

 

 

 

 

 

 

 

 

 

T_RAS

 

 

 

T_RC

 

T_RRD

 

Rsvd

T_WTR

R/W-0x1F

 

 

R/W-0x1F

 

R/W-0x7

 

R-0

R/W-0x3

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

 

 

 

 

 

 

Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions

 

 

 

Bit

Field

Value

Description

 

 

 

 

31-25

T_RFC

 

These bits specify the minimum number of DDR2CLKOUT cycles from a refresh or load mode

 

 

 

command to a refresh or activate command, minus one. The value for these bits can be derived

 

 

 

from the trfc AC timing parameter in the DDR2 memory section of the device-specific data manual.

 

 

 

Calculate using this formula:

 

 

 

T_RFC = (trfc/DDR2CLKOUT) - 1

 

 

 

 

24-22

T_RP

 

These bits specify the minimum number of DDR2CLKOUT cycles from a precharge command to a

 

 

 

refresh or activate command, minus 1. The value for these bits can be derived from the trp AC

 

 

 

timing parameter in the DDR2 memory section of the device-specific data manual. Calculate using

 

 

 

the formula:

 

 

 

T_RP = (trp/DDR2CLKOUT) - 1

 

 

 

 

21-19

T_RCD

 

These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to a

 

 

 

read or write command, minus 1. The value for these bits can be derived from the trcd AC timing

 

 

 

parameter in the DDR2 memory section of the device-specific data manual. Calculate using the

 

 

 

formula:

 

 

 

T_RCD = (trcd/DDR2CLKOUT) - 1

 

 

 

 

18-16

T_WR

 

These bits specify the minimum number of DDR2CLKOUT cycles from the last write transfer to a

 

 

 

precharge command, minus 1. The value for these bits can be derived from the twr AC timing

 

 

 

parameter in the DDR2 memory section of the device-specific data manual. Calculate using the

 

 

 

formula:

 

 

 

T_WR = (twr/DDR2CLKOUT) - 1

 

 

 

The SDRAM initialization sequence will be started when the value of this field is changed from the

 

 

 

previous value and the DDR2_ENABLE in SDCFG is equal to 1.

 

 

 

 

15-11

T_RAS

 

These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to a

 

 

 

precharge command, minus 1. The value for these bits can be derived from the tras AC timing

 

 

 

parameter in the DDR2 memory section of the device-specific data manual. Calculate using this

 

 

 

formula:

 

 

 

T_RAS = (tras/DDR2CLKOUT) - 1

 

 

 

T_RAS must be greater than or equal to T_RCD.

 

 

 

 

10-6

T_RC

 

These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to an

 

 

 

activate command, minus 1. The value for these bits can be derived from the trc AC timing

 

 

 

parameter in the DDR2 memory section of the device-specific data manual. Calculate using this

 

 

 

formula:

 

 

 

T_RC = (trc/DDR2CLKOUT) - 1

 

 

 

 

44

C6455/C6454 DDR2 Memory Controller

SPRU970G – December 2005 – Revised June 2011

 

 

Submit Documentation Feedback

Copyright © 2005–2011, Texas Instruments Incorporated

Page 43 Page 45
Image 44
Page 43 Page 45
Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control DDR2 Memory Controller Signal Descriptions Pin DescriptionDDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol DescriptionsMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandRefresh Mode Refresh CommandActv Command Activation ActvDcab Command Deactivation Dcab and DeacDeac Command Read Command DDR2 Read CommandWrite WRT Command Memory Width, Byte Alignment, and EndiannessAddressable Memory Ranges Address Type Generated by DDR2Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Scheduling Possible Race ConditionRefresh Urgency Levels Urgency Level DescriptionSelf-Refresh Mode Reset ConsiderationsDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated by11.1 DDR2 Sdram Device Mode Register Configuration Values DDR2 Sdram Mode Register ConfigurationDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field11.2 DDR2 Sdram Initialization After Reset 11.3 DDR2 Sdram Initialization After Register ConfigurationInterrupt Support Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Configuration Register Sdcfg Sdcfg ConfigurationProgramming the Sdram Refresh Control Register Sdrfc FieldDDR2 Memory Refresh Specification Sdrfc ConfigurationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationSDTIM2 Configuration Dmcctl ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionRegister Description DDR2 Memory Controller RegistersOffset Bit Field Value Description Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions DDR2 Memory Controller Status Register Dmcstat IfrdySdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsSdram Timing 1 Register SDTIM1 Sdram Timing 1 Register SDTIM1 Field DescriptionsTrfc TRP Trcd TWR Tras TRC TrrdUsing this formula Sdram Timing 2 Register SDTIM2 Sdram Timing 2 Register SDTIM2 Field DescriptionsTodt Txsnr Txsrd Trtp TckePrioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History Products Applications DSPRfid TI E2E Community Home
Top Page Image Contents