Texas Instruments TMS320C6455 manual Address Mapping, Bit Field Bit Value Bit Description, Ibank

Page 21

www.ti.com

Peripheral Architecture

Figure 10 shows the byte lanes used on the DDR2 memory controller. The external memory is always right aligned on the data bus.

Figure 10. Byte Alignment

 

DDR2 memory controller data bus

 

DED[31:24]

DED[23:16]

DED[15:8]

DED[7:0]

(Byte Lane 3)

(Byte Lane 2)

(Byte Lane 1)

(Byte Lane 0)

 

 

 

 

32-bit memory device

16-bit memory device

The DDR2 memory controller supports both little endian and big endian formats. The endianness mode determines whether byte lane 0 (DED[7:0]) is accessed as byte address 0 (little endian) or as byte address N (big endian), where 2n is the memory width in bytes. Similarly, byte lane N is addresses as either byte address 0 (big endian) or as byte address N (little endian).

The DDR2 memory controller uses the endianness mode being used by the rest of the DSP. The endianness mode of the DSP is set during device reset (for more details, see the device-specific data manual. The endianness mode of the DDR2 memory controller is shown on the BE bit of the DDR2 memory controller status register (DMCSTAT); BE = 1 indicates big endian mode and BE = 0 indicates little endian mode.

2.6Address Mapping

The DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory. This statement is true regardless of the number of memory devices located on the chip select space. The DDR2 memory controller receives DDR2 memory access requests along with a 32-bit logical address from the rest of the system. In turn, DDR2 memory controller uses the logical address to generate a row/page, column, bank address, and chip selects for the DDR2 SDRAM. The number of column and bank address bits used is determined by the IBANK and PAGESIZE fields. The chip selection pins used are determined by the DCE0 field (see Table 5). The DDR2 memory controller uses up to 14 bits for the row/page address.

Table 5. Bank Configuration Register Fields for Address Mapping

Bit Field

Bit Value

Bit Description

IBANK

 

Defines the number of internal banks on the external DDR2 memory.

 

0

1 bank

 

1h

2 banks

 

2h

4 banks

 

3h

8 banks

PAGESIZE

 

Defines the page size of each page of the external DDR2 memory.

 

0

256 words (requires 8 column address bits)

 

1h

512 words (requires 9 column address bits)

 

2h

1024 words (requires 10 column address bits)

 

3h

2048 words (requires 11 column address bits)

 

 

 

SPRU970G – December 2005 – Revised June 2011

C6455/C6454 DDR2 Memory Controller

21

Submit Documentation Feedback

 

 

Copyright © 2005–2011, Texas Instruments Incorporated

Page 20 Page 22
Image 21
Page 20 Page 22
Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map Pin Description DDR2 Memory Controller Signal DescriptionsTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsRefresh Command Refresh ModeActivation Actv Actv CommandDeactivation Dcab and Deac Dcab CommandDeac Command DDR2 Read Command Read CommandMemory Width, Byte Alignment, and Endianness Write WRT CommandAddressable Memory Ranges Address Type Generated by DDR2Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level DescriptionReset Considerations Self-Refresh ModeDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated byDDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc FieldSdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationDmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionDDR2 Memory Controller Registers OffsetRegister Description Module ID and Revision Register Midr Module ID and Revision Register Midr Field DescriptionsBit Field Value Description Ifrdy DDR2 Memory Controller Status Register DmcstatSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcSdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC TrrdUsing this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Txsnr Txsrd Trtp TckeBurst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History DSP Products ApplicationsRfid TI E2E Community Home
Top Page Image Contents