Texas Instruments TMS320C6455 manual Purpose of the Peripheral, Features, Functional Block Diagram

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User's Guide

SPRU970G – December 2005 – Revised June 2011

C6455/C6454 DDR2 Memory Controller

1 Introduction

1.1Purpose of the Peripheral

The DDR2 memory controller is used to interface with JESD79-2B standard compliant DDR2 SDRAM devices. Memory types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. The DDR2 memory controller SDRAM can be used for program and data storage.

1.2Features

The DDR2 memory controller supports the following features:

•JESD79-2B standard compliant DDR2 SDRAM

•512M byte memory space

•Data bus width of 32 or 16 bits

•CAS latencies: 2, 3, 4, and 5

•Internal banks: 1, 2, 4, and 8

•Burst length: 8

•Burst type: sequential

•1 CE signal

•Page sizes: 256, 512, 1024, and 2048

•SDRAM autoinitialization

•Self-refresh mode

•Prioritized refresh

•Programmable refresh rate and backlog counter

•Programmable timing parameters

•Little endian and big endian transfers

1.3Functional Block Diagram

The DDR2 memory controller is the main interface to external DDR2 memory (see Figure 1). Master peripherals, such as the EDMA controller and the CPU can access the DDR2 memory controller through the switched central resource (SCR). The DDR2 memory controller performs all memory-related background tasks such as opening and closing banks, refreshes, and command arbitration.

SPRU970G – December 2005 – Revised June 2011C6455/C6454 DDR2 Memory Controller 9

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map Pin Description DDR2 Memory Controller Signal DescriptionsTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsRefresh Command Refresh ModeActivation Actv Actv CommandDeactivation Dcab and Deac Dcab CommandDeac Command DDR2 Read Command Read CommandMemory Width, Byte Alignment, and Endianness Write WRT CommandAddressable Memory Ranges Address Type Generated by DDR2Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level DescriptionReset Considerations Self-Refresh ModeDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated byDDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc FieldSdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationDmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionDDR2 Memory Controller Registers OffsetRegister Description Module ID and Revision Register Midr Module ID and Revision Register Midr Field DescriptionsBit Field Value Description Ifrdy DDR2 Memory Controller Status Register DmcstatSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcSdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC TrrdUsing this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Txsnr Txsrd Trtp TckeBurst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History DSP Products ApplicationsRfid TI E2E Community Home