Texas Instruments TMS320C6455 manual Read This First

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8	Read This First	SPRU970G – December 2005 – Revised June 2011
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Copyright © 2005–2011, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control DDR2 Memory Controller Signal Descriptions Pin DescriptionDDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol DescriptionsMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandRefresh Mode Refresh CommandActv Command Activation ActvDcab Command Deactivation Dcab and DeacDeac Command Read Command DDR2 Read CommandWrite WRT Command Memory Width, Byte Alignment, and EndiannessAddressable Memory Ranges Address Type Generated by DDR2Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Scheduling Possible Race ConditionRefresh Urgency Levels Urgency Level DescriptionSelf-Refresh Mode Reset ConsiderationsDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated by11.1 DDR2 Sdram Device Mode Register Configuration Values DDR2 Sdram Mode Register ConfigurationDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field11.2 DDR2 Sdram Initialization After Reset 11.3 DDR2 Sdram Initialization After Register ConfigurationInterrupt Support Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Configuration Register Sdcfg Sdcfg ConfigurationProgramming the Sdram Refresh Control Register Sdrfc FieldDDR2 Memory Refresh Specification Sdrfc ConfigurationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationSDTIM2 Configuration Dmcctl ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionRegister Description DDR2 Memory Controller RegistersOffset Bit Field Value Description Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions DDR2 Memory Controller Status Register Dmcstat IfrdySdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsSdram Timing 1 Register SDTIM1 Sdram Timing 1 Register SDTIM1 Field DescriptionsTrfc TRP Trcd TWR Tras TRC TrrdUsing this formula Sdram Timing 2 Register SDTIM2 Sdram Timing 2 Register SDTIM2 Field DescriptionsTodt Txsnr Txsrd Trtp TckePrioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History Products Applications DSPRfid TI E2E Community Home