Texas Instruments TMS320C6455 manual DDR2 Memory Controller Signal Descriptions, Pin Description

Page 12

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Figure 2. DDR2 Memory Controller Signals

 

 

 

 

 

 

 

 

 

 

DDR2CLKOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR2CLKOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSDCKE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DCE0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSDWE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSDRAS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR2

 

 

 

DSDCAS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSDDQM[3:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSDDQS[3:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSDDQS[3:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DBA[2:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEA[13:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DED[31:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEODT[1:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSDDQGATE[3:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREFSSTL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDRSLRATE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 1. DDR2 Memory Controller Signal Descriptions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DED[31:0]

Bidirectional data bus. Input for data reads and output for data writes.

 

DEA[13:0]

External address output.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Active-low chip enable for memory space CE0.

 

is used to enable the DDR2 SDRAM memory

 

DCE0

DCE0

 

 

 

 

 

 

 

 

device during external memory accesses. The

DCE0

pin stays low throughout the operation of the

 

 

 

 

 

 

 

 

DDR2 memory controller; it never goes high. Note that this behavior does not affect the ability of the

 

 

 

 

 

 

 

 

DDR2 memory controller to access DDR2 SDRAM memory devices.

 

 

 

 

Active-low output data mask.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSDDQM[3:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR2CLKOUT

Differential clock outputs.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR2CLKOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSDCKE

Clock enable (used for self-refresh mode).

 

 

 

 

 

 

Active-low column address strobe.

 

DSDCAS

 

 

 

 

 

 

Active-low row address strobe.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSDRAS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Active-low write enable.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSDWE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSDDQS[3:0]/

Differential data strobe bidirectional signals.

 

DSDDQS[3:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEODT[1:0]

On-die termination signals to external DDR2 SDRAM. These pins are reserved for future use and

 

 

 

 

 

 

 

 

should not be connected to the DDR2 SDRAM.

 

DBA[2:0]

Bank-address control outputs.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSDDQGATE[3:0]

Data strobe gate pins. These pins are used as a timing reference during memory reads. The

 

 

 

 

 

 

 

 

DSDDQGATE0 and DSDDQGATE2 pins should be routed out and connected to the DSDDQGATE1

 

 

 

 

 

 

 

 

and DSDDQGATE3 pins, respectively. For more routing requirements on these pins, see the

 

 

 

 

 

 

 

 

device-specific data manual.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREFSSTL

DDR2 Memory Controller reference voltage. This voltage must be supplied externally. For more details,

 

 

 

 

 

 

 

 

see the device-specific data manual.

 

DDRSLRATE

Pulling the DDRSLRATE input pin low selects the normal slew rate. If pulled high, the slew rate is

 

 

 

 

 

 

 

 

reduced by 33%. For normal full-speed operation, the DDRSLRATE should be pulled low.This pin

 

 

 

 

 

 

 

 

needs to be pulled low or high at all times (it is not latched).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12 C6455/C6454 DDR2 Memory Controller

SPRU970G – December 2005 – Revised June 2011

 

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Copyright © 2005–2011, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map DDR2 Memory Controller Signal Descriptions Pin DescriptionDDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol DescriptionsMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandRefresh Mode Refresh CommandActv Command Activation ActvDcab Command Deactivation Dcab and DeacDeac Command Read Command DDR2 Read CommandWrite WRT Command Memory Width, Byte Alignment, and EndiannessAddressable Memory Ranges Address Type Generated by DDR2Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Scheduling Possible Race ConditionRefresh Urgency Levels Urgency Level DescriptionSelf-Refresh Mode Reset ConsiderationsDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated by11.1 DDR2 Sdram Device Mode Register Configuration Values DDR2 Sdram Mode Register ConfigurationDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field11.2 DDR2 Sdram Initialization After Reset 11.3 DDR2 Sdram Initialization After Register ConfigurationInterrupt Support Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Configuration Register Sdcfg Sdcfg ConfigurationProgramming the Sdram Refresh Control Register Sdrfc FieldDDR2 Memory Refresh Specification Sdrfc ConfigurationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationSDTIM2 Configuration Dmcctl ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionDDR2 Memory Controller Registers OffsetRegister Description Module ID and Revision Register Midr Module ID and Revision Register Midr Field DescriptionsBit Field Value Description DDR2 Memory Controller Status Register Dmcstat IfrdySdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsSdram Timing 1 Register SDTIM1 Sdram Timing 1 Register SDTIM1 Field DescriptionsTrfc TRP Trcd TWR Tras TRC TrrdUsing this formula Sdram Timing 2 Register SDTIM2 Sdram Timing 2 Register SDTIM2 Field DescriptionsTodt Txsnr Txsrd Trtp TckeBurst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History Products Applications DSPRfid TI E2E Community Home
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