Texas Instruments TMS320C6455 manual Command Starvation

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Peripheral Architecture

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Next, the DDR2 memory controller examines each of the commands selected by the individual masters and performs the following reordering:

•Among all pending reads, selects reads to rows already open. Among all pending writes, selects writes to rows already open.

•Selects the highest priority command from pending reads and writes to open rows. If multiple commands have the highest priority, then the DDR2 memory controller selects the oldest command.

The DDR2 memory controller may now have a final read and write command. If the Read FIFO is not full, then the read command will be performed before the write command, otherwise the write command will be performed first.

Besides commands received from on-chip resources, the DDR2 memory controller also issues refresh commands. The DDR2 memory controller attempts to delay refresh commands as long as possible to maximize performance while meeting the SDRAM refresh requirements. As the DDR2 memory controller issues read, write, and refresh commands to DDR2 SDRAM device, it follows the following priority scheme:

1.(Highest) Refresh request resulting from the Refresh Must level of urgency (see Section 2.8) being reached

2.Read request without a higher priority write (selected from above reordering algorithm)

3.Refresh request resulting from the Refresh Need level of urgency (see Section 2.8) being reached

4.Write request (selected from above reordering algorithm)

5.Refresh request resulting from Refresh May level of urgency (see Section 2.8) being reached

6.(Lowest) Request to enter self-refresh mode

The following results from the above scheduling algorithm:

•All writes from a single master will complete in order

•All reads from a single master will complete in order

•From the same master, any read to the same location (or within 2048 bytes) as a previous write will complete in order

2.7.2Command Starvation

The reordering and scheduling rules listed above may lead to command starvation, which is the prevention of certain commands from being processed by the DDR2 memory controller. Command starvation results from the following conditions:

•A continuous stream of high-priority read commands can block a low-priority write command

•A continuous stream of DDR2 SDRAM commands to a row in an open bank can block commands to the closed row in the same bank.

To avoid these conditions, the DDR2 memory controller can momentarily raise the priority of the oldest command in the command FIFO after a set number of transfers have been made. The PRIO_RAISE field in the Burst Priority Register (BPRIO) sets the number of the transfers that must be made before the DDR2 memory controller will raise the priority of the oldest command.

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C6455/C6454 DDR2 Memory Controller

SPRU970G – December 2005 – Revised June 2011

 

 

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control DDR2 Memory Controller Signal Descriptions Pin DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandRefresh Mode Refresh CommandActv Command Activation ActvDcab Command Deactivation Dcab and DeacDeac Command Read Command DDR2 Read CommandAddressable Memory Ranges Write WRT CommandMemory Width, Byte Alignment, and Endianness Address Type Generated by DDR2Bit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping IbankLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Urgency Levels Refresh SchedulingPossible Race Condition Urgency Level DescriptionDevice and DDR2 Memory Controller Reset Relationship Self-Refresh ModeReset Considerations DDR2 Memory Controller Reset Effect Initiated byDDR2 Sdram Extended Mode Register 1 Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration Mode Register FieldInterrupt Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Refresh Control Register Sdrfc Programming the Sdram Configuration Register SdcfgSdcfg Configuration FieldConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 DDR2 Memory Refresh SpecificationSdrfc Configuration SDTIM1 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter SDTIM2 ConfigurationDmcctl Configuration Name DescriptionRegister Description DDR2 Memory Controller RegistersOffset Bit Field Value Description Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions DDR2 Memory Controller Status Register Dmcstat IfrdySdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsTrfc TRP Trcd TWR Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Tras TRC TrrdUsing this formula Todt Txsnr Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Txsrd Trtp TckePrioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History Rfid Products ApplicationsDSP TI E2E Community Home
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