Texas Instruments TMS320C6455 manual Connecting to Two 8-Bit DDR2 Sdram Devices

Page 34

Using the DDR2 Memory Controller

www.ti.com

Figure 18. Connecting to Two 8-Bit DDR2 SDRAM Devices

DDR2CLKOUT
DDR2CLKOUT
	DSDCKE
DDR2	DCE0
Memory	DCE0
Memory	DSDWE
Controller	DSDWE
Controller	DSDRAS
	DSDRAS
	DSDCAS
	DSDDQM0
	DSDDQS0
	DSDDQS0
		VREF
	DBA[2:0]
	DEA[13:0]
	DED[7:0]
	DSDDQM1
	DSDDQS1
	DSDDQS1
	DED[15:8]
	ODT0
	ODT1
	VREFSSTL
DDRSLRATE		VDD
DSDDQGATE0(A)
DSDDQGATE1(A)
DSDDQGATE2(A)
DSDDQGATE3(A)

CK

CK

CKE

								DDR2
	CS							DDR2
	CS							Memory

	WE
	WE							x8-bit
								x8-bit
	RAS

	CAS

	DM
	DQS

	DQS
	RDQS

	RDQS
	BA[2:0]
	A[13:0]
	DQ[7:0]
	ODT
	VREF
	CK

	CK
	CKE
								DDR2
	CS							DDR2
	CS							Memory

	WE
	WE							x8-bit
								x8-bit
	RAS

	CAS
	DM
	DQS

	DQS
	RDQS

	RDQS
	BA[2:0]
	A[13:0]
	DQ[7:0]
	ODT
	VREF

AThese pins are used as a timing reference during memory reads. For routing rules, see the device-specific data manual.

34	C6455/C6454 DDR2 Memory Controller	SPRU970G – December 2005 – Revised June 2011
		Submit Documentation Feedback

Copyright © 2005–2011, Texas Instruments Incorporated

Image 34

Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map DDR2 Memory Controller Signal Descriptions Pin DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandRefresh Mode Refresh CommandActv Command Activation ActvDcab Command Deactivation Dcab and DeacDeac Command Read Command DDR2 Read CommandAddressable Memory Ranges Write WRT CommandMemory Width, Byte Alignment, and Endianness Address Type Generated by DDR2Bit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping IbankLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Urgency Levels Refresh SchedulingPossible Race Condition Urgency Level DescriptionDevice and DDR2 Memory Controller Reset Relationship Self-Refresh ModeReset Considerations DDR2 Memory Controller Reset Effect Initiated byDDR2 Sdram Extended Mode Register 1 Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration Mode Register FieldInterrupt Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Edma Event Support Using the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Refresh Control Register Sdrfc Programming the Sdram Configuration Register SdcfgSdcfg Configuration FieldConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 DDR2 Memory Refresh SpecificationSdrfc Configuration SDTIM1 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter SDTIM2 ConfigurationDmcctl Configuration Name DescriptionOffset DDR2 Memory Controller RegistersRegister Description Module ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrBit Field Value Description DDR2 Memory Controller Status Register Dmcstat IfrdySdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsTrfc TRP Trcd TWR Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Tras TRC TrrdUsing this formula Todt Txsnr Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Txsrd Trtp TckeBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History Rfid Products ApplicationsDSP TI E2E Community Home