Texas Instruments TMS320C6455 manual Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram

Page 22

Peripheral Architecture

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Figure 11 and Figure 12 show how the logical address bits map to the row, column, bank, and chip select bits all combinations of IBANK and PAGESIZE values. Note that the upper three bits of the logical address cannot be used for memory addressing, as the DDR2 memory controller has a maximum addressable memory range of 512M bytes.

The DDR2 memory controller address pins provide the row and column address to the DDR2 SDRAM, thus the DDR2 memory controller appropriately shifts the logical address during row and column address selection. The bank address is driven to the DDR2 SDRAM using the bank address pins. The two lower bits of the logical address decode the value of the byte enable pins (only used for accesses less than the width of the DDR2 memory controller data bus).

Figure 11. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM

SDCFG Bit

 

 

 

 

 

 

 

 

Logical Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IBANK

PAGESIZE

31:29

28

27

26

25

 

24

23

22:17

16

15

14

13

 

12

 

11

 

10

 

9:2

0

0

X

X

X

X

X

 

X

 

 

 

 

nrb=14

 

 

 

 

 

 

 

 

ncb=8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

X

X

X

X

X

 

 

 

 

 

nrb=14

 

 

 

 

 

 

 

nbb=1

 

ncb=8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

0

X

X

X

X

 

 

 

 

 

nrb=14

 

 

 

 

 

 

 

nbb=2

 

ncb=8

3

0

X

X

X

 

 

 

 

 

nrb=14

 

 

 

 

 

 

 

nbb=3

 

ncb=8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

X

X

X

X

X

 

 

 

 

 

nrb=14

 

 

 

 

 

 

 

 

ncb=9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

X

X

X

X

 

 

 

 

 

nrb=14

 

 

 

 

 

 

nbb=1

 

ncb=9

2

1

X

X

X

 

 

 

 

 

nrb=14

 

 

 

 

 

 

nbb=2

 

 

ncb=9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

1

X

X

 

 

 

 

 

nrb=14

 

 

 

 

 

 

nbb=3

 

 

ncb=9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

2

X

X

X

X

 

 

 

 

 

nrb=14

 

 

 

 

 

 

 

 

ncb=10

1

2

X

X

X

 

 

 

 

 

nrb=14

 

 

 

 

 

nbb=1

 

 

 

ncb=10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

2

X

X

 

 

 

 

 

nrb=14

 

 

 

 

 

nbb=2

 

 

 

ncb=10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

2

X

 

 

 

 

 

nrb=14

 

 

 

 

 

nbb=3

 

 

 

ncb=10

0

3

X

X

X

 

 

 

 

 

nrb=14

 

 

 

 

 

 

 

 

ncb=11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

3

X

X

 

 

 

 

 

nrb=14

 

 

 

 

nbb=1

 

 

 

 

ncb=11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

3

X

 

 

 

 

 

nrb=14

 

 

 

 

nbb=2

 

 

 

 

ncb=11

 

 

3

3

X

 

 

 

 

nrb=13

 

 

 

 

nbb=3

 

 

 

 

 

ncb=11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LEGEND: nrb = number of row address bits; ncb = number of column address bits; nbb = number of bank address bits.

Figure 12. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM

SDCFG Bit

 

 

 

 

 

 

 

Logical Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IBANK

PAGESIZE

31:29

28

27

26

25

24

23

22

21:16

15

14

13

12

11

10

9

8:1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

X

X

X

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

ncb=8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

X

X

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=1

ncb=8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

0

X

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=2

ncb=8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

0

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

 

nbb=3

 

ncb=8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

X

X

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

ncb=9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

X

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=1

ncb=9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

1

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=2

ncb=9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

1

X

X

X

 

 

 

 

nrb=14

 

 

 

 

 

nbb=3

 

ncb=9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

2

X

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

 

ncb=10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

2

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=1

 

ncb=10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

2

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=2

 

ncb=10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

2

X

X

 

 

 

 

nrb=14

 

 

 

 

 

nbb=3

 

 

ncb=10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

3

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

 

ncb=11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

3

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=1

 

ncb=11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

3

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=2

 

ncb=11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

3

X

 

 

 

 

nrb=14

 

 

 

 

 

nbb=3

 

 

ncb=11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LEGEND: nrb = number of row address bits; ncb = number of column address bits; nbb = number of bank address bits.

Figure 11 shows how the DSP memory map is partitioned into columns, rows, and banks. Note that during a linear access, the DDR2 memory controller increments the column address as the logical address increments. When the DDR2 memory controller reaches a page/row boundary, it moves onto the same page/row in the next bank. This movement continues until the same page has been accessed in all banks. To the DDR2 SDRAM, this process looks as shown on Figure 14.

By traversing across banks while remaining on the same row/page, the DDR2 memory controller maximizes the number of activated banks for a linear access. This results in the maximum number of open pages when performing a linear access being equal to the number of banks. Note that the DDR2 memory controller never opens more than one page per bank.

22

C6455/C6454 DDR2 Memory Controller

SPRU970G – December 2005 – Revised June 2011

 

 

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Copyright © 2005–2011, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map DDR2 Memory Controller Signal Descriptions Pin DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandRefresh Mode Refresh CommandActv Command Activation ActvDcab Command Deactivation Dcab and DeacDeac Command Read Command DDR2 Read CommandAddressable Memory Ranges Write WRT CommandMemory Width, Byte Alignment, and Endianness Address Type Generated by DDR2Bit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping IbankLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Urgency Levels Refresh SchedulingPossible Race Condition Urgency Level DescriptionDevice and DDR2 Memory Controller Reset Relationship Self-Refresh ModeReset Considerations DDR2 Memory Controller Reset Effect Initiated byDDR2 Sdram Extended Mode Register 1 Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration Mode Register FieldInterrupt Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Refresh Control Register Sdrfc Programming the Sdram Configuration Register SdcfgSdcfg Configuration FieldConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 DDR2 Memory Refresh SpecificationSdrfc Configuration SDTIM1 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter SDTIM2 ConfigurationDmcctl Configuration Name DescriptionOffset DDR2 Memory Controller RegistersRegister Description Module ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrBit Field Value Description DDR2 Memory Controller Status Register Dmcstat IfrdySdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsTrfc TRP Trcd TWR Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Tras TRC TrrdUsing this formula Todt Txsnr Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Txsrd Trtp TckeBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History Rfid Products ApplicationsDSP TI E2E Community Home
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