Texas Instruments TMS320C6455 manual Sdram Configuration Register Sdcfg

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DDR2 Memory Controller Registers

4.3SDRAM Configuration Register (SDCFG)

The SDRAM configuration register (SDCFG) contains fields that program the DDR2 memory controller to meet the specification of the DDR2 memory. These fields configure the DDR2 memory controller to match the data bus width, CAS latency, number of internal banks, and page size of the external DDR2 memory. Bits 0-14 of the SDCFG register are only writeable when the TIMUNLOCK bit is set to 0 (unlocked). for more information on initializing the configuration registers of the DDR2 memory controller, see

Section 2.11.1. The SDCFG register is shown in Figure 21 and described in Table 20.

Figure 21. SDRAM Configuration Register (SDCFG)

31

 

 

 

 

 

 

 

24

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

R-0x0

 

 

 

 

23

22

 

 

19

18

17

16

 

 

 

 

 

 

 

 

 

 

BOOT_

 

Reserved

 

 

 

DDR_DRIVE

Reserved

UNLOCK

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W-0

 

R/W-0xA

 

 

 

R-0

 

R-0x3

15

14

13

12

11

 

9

8

 

 

 

 

 

 

 

 

 

 

TIMUNLOCK

NM

Reserved

 

 

 

CL

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

R/W-0

R/W-0

R-0x0

 

 

 

R/W-0x5

 

 

R-0x0

7

6

 

4

3

2

 

0

 

 

 

 

 

 

 

 

 

 

Reserved

 

IBANK

 

 

Reserved

 

PAGESIZE

 

 

 

 

 

 

 

 

 

 

 

 

R-0x0

 

R/W-0x2

 

 

R-0x0

 

R/W-0x0

 

 

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 20. SDRAM Configuration Register (SDCFG) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

31-24

Reserved

 

Reserved. Writes to this register must keep these bits at their default values.

 

 

 

 

23

BOOT_UNLOCK

 

Boot unlock bit. Controls write access to bits 16-22 and 27 of this register.

 

 

0

Writes to bits 22:16 of this register are not permitted.

 

 

1

Writes to bits 22:16 of this register are allowed.

 

 

 

 

22-19

Reserved

 

Reserved. Writes to this register must keep these bits at their default value.

 

 

 

 

18

DDR_DRIVE

 

DDR2 SDRAM drive strength. This bit is used to select the drive strength used by the DDR2

 

 

 

SDRAM. This bit is writeable only when BOOT_UNLOCK is unlocked (set to 1).

 

 

0

Normal drive strength.

 

 

1

Weak (60%) drive strength.

 

 

 

 

17-16

Reserved

 

Reserved. Writes to this register must keep these bits at their default value.

 

 

 

 

15

TIMUNLOCK

 

Timing unlock bit. Controls write access for the SDRAM Timing Register (SDTIM1) and

 

 

 

SDRAM Timing Register 2 (SDTIM2). A write to this bit causes the DDR2 Memory Controller

 

 

 

to start the SDRAM initialization sequence.

 

 

0

Register fields in the SDTIM1 and SDTIM2 registers may not be changed.

 

 

1

Register fields in the SDTIM1 and SDTIM2 registers may be changed.

 

 

 

 

14

NM

 

DDR2 data bus width. A write to this bit will cause the DDR2 Memory Controller to start the

 

 

 

SDRAM initialization sequence.

 

 

0

32-bit bus width.

 

 

1

16-bit bus width

 

 

 

 

13-12

Reserved

 

Reserved. The reserved bit location is always read as 0. A value written to this field has no

 

 

 

effect.

 

 

 

 

SPRU970G – December 2005 – Revised June 2011

C6455/C6454 DDR2 Memory Controller

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Copyright © 2005–2011, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control Pin Description DDR2 Memory Controller Signal DescriptionsTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsRefresh Command Refresh ModeActivation Actv Actv CommandDeactivation Dcab and Deac Dcab CommandDeac Command DDR2 Read Command Read CommandMemory Width, Byte Alignment, and Endianness Write WRT CommandAddressable Memory Ranges Address Type Generated by DDR2Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level DescriptionReset Considerations Self-Refresh ModeDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated byDDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc FieldSdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationDmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionRegister Description DDR2 Memory Controller RegistersOffset Bit Field Value Description Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions Ifrdy DDR2 Memory Controller Status Register DmcstatSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcSdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC TrrdUsing this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Txsnr Txsrd Trtp TckePrioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History DSP Products ApplicationsRfid TI E2E Community Home
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