Texas Instruments TMS320C6455 manual Sdram Refresh Control Register Sdrfc

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DDR2 Memory Controller Registers

4.4SDRAM Refresh Control Register (SDRFC)

The SDRAM refresh control register (SDRFC) is used to configure the DDR2 memory controller to:

•Enter and Exit the self-refresh state.

•Meet the refresh requirement of the attached DDR2 device by programming the rate at which the DDR2 memory controller issues autorefresh commands.

The SDRFC is shown in Figure 22 and described in Table 21.

			Figure 22. SDRAM Refresh Control Register (SDRFC)
31	30	29	16

SR	Rsvd		Reserved

R/W-	R/W-		R-0x0
0x0	0x0
15			0

			REFRESH_RATE
			R/W-0x753

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 21. SDRAM Refresh Control Register (SDRFC) Field Descriptions

Bit	Field	Value	Description

31	SR		Self-refresh bit. Writing a 1 to this bit will cause connected SDRAM devices to be place into Self
			Refresh mode and the DDR2 Memory Controller to enter the Self Refresh state.
		0	Exit self-refresh mode.
		1	Enter self-refresh mode.

30-16	Reserved		Reserved. Writes to this register must keep this field at its default value.

15-0	REFRESH_RATE		Refresh rate bits. The value in this field is used to define the rate at which connected SDRAM
			devices will be refreshed as follows:
			SDRAM refresh rate = DDR2CLKOUT clock rate / REFRESH_RATE
			Writing a value less than 0x0100 to this field will cause it to be loaded with 2 * T_RFC value from
			the SDRAM Timing 1 Register.

SPRU970G – December 2005 – Revised June 2011	C6455/C6454 DDR2 Memory Controller	43
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map Pin Description DDR2 Memory Controller Signal DescriptionsProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsRefresh Command Refresh ModeActivation Actv Actv CommandDeactivation Dcab and Deac Dcab CommandDeac Command DDR2 Read Command Read CommandAddress Type Generated by DDR2 Write WRT CommandMemory Width, Byte Alignment, and Endianness Addressable Memory RangesIbank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit DescriptionLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency LevelsDDR2 Memory Controller Reset Effect Initiated by Self-Refresh ModeReset Considerations Device and DDR2 Memory Controller Reset RelationshipMode Register Field 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 ConfigurationEdma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Field Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register SdrfcSDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet ParameterOffset DDR2 Memory Controller RegistersRegister Description Module ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrBit Field Value Description Ifrdy DDR2 Memory Controller Status Register DmcstatSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcTras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWRUsing this formula Txsrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt TxsnrBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History TI E2E Community Home Products ApplicationsDSP Rfid