Texas Instruments TMS320C6455 manual Protocol Descriptions, DDR2 Sdram Commands, Command Function

Page 13

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Peripheral Architecture

2.4Protocol Description(s)

The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2. Table 3 shows the signal truth table for the DDR2 SDRAM commands.

 

Table 2. DDR2 SDRAM Commands

 

 

Command

Function

 

 

ACTV

Activates the selected bank and row.

DCAB

Precharge all command. Deactivates (precharges) all banks.

DEAC

Precharge single command. Deactivates (precharges) a single bank.

DESEL

Device Deselect.

EMRS

Extended Mode Register set. Allows altering the contents of the mode register.

MRS

Mode register set. Allows altering the contents of the mode register.

NOP

No operation.

Power Down

Power down mode.

READ

Inputs the starting column address and begins the read operation.

READ with

Inputs the starting column address and begins the read operation. The read operation is followed by a

autoprecharge

precharge.

REFR

Autorefresh cycle.

SLFREFR

Self-refresh mode.

WRT

Inputs the starting column address and begins the write operation.

WRT with

Inputs the starting column address and begins the write operation. The write operation is followed by a

autoprecharge

precharge.

 

 

Table 3. Truth Table for DDR2 SDRAM Commands

DDR2 SDRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signals

 

CKE

 

 

CS

 

 

 

RAS

 

 

 

CAS

 

 

 

WE

 

BA[2:0]

A[13:11, 9:0]

A10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSDCKE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR2 Memory

Previous

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Controller Signals

Cycles

 

Current Cycle

 

DCE0

 

 

DSDRAS

 

 

DSDCAS

 

 

DSDWE

 

DBA[2:0]

DEA[13:11, 9:0]

DEA[10]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ACTV

H(1)

 

H

 

 

L

 

 

L

 

 

H

 

 

H

Bank

Row Address

 

DCAB

H

 

H

 

 

L

 

 

L

 

 

H

 

 

L

X

X

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEAC

H

 

H

 

 

L

 

 

L

 

 

H

 

 

L

Bank

X

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MRS

H

 

H

 

 

L

 

 

L

 

 

L

 

 

L

BA(2)

OP Code

 

EMRS

H

 

H

 

 

L

 

 

L

 

 

L

 

 

L

BA

OP Code

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ

H

 

H

 

 

L

 

 

H

 

 

L

 

 

H

BA

Column Address

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ with

H

 

H

 

 

L

 

 

H

 

 

L

 

 

H

BA

Column Address

H

precharge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRT

H

 

H

 

 

L

 

 

H

 

 

L

 

 

L

BA

Column Address

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRT with precharge

H

 

H

 

 

L

 

 

H

 

 

L

 

 

L

BA

Column Address

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REFR

H

 

H

 

 

L

 

 

L

 

 

L

 

 

H

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLFREFR

H

 

L

 

 

L

 

 

L

 

 

L

 

 

H

X

X

X

entry

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLFREFR

L

 

H

 

 

H

 

 

X

 

 

X

 

 

X

X

X

X

exit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

H

 

 

H

 

 

H

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP

H

 

X

 

 

L

 

 

H

 

 

H

 

 

H

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DESEL

H

 

X

 

 

H

 

 

X

 

 

X

 

 

X

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power-down

H

 

L

 

 

H

 

 

X

 

 

X

 

 

X

X

X

X

entry

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

H

 

 

H

 

 

H

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power-down

L

 

H

 

 

H

 

 

X

 

 

X

 

 

X

X

X

X

exit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

H

 

 

H

 

 

H

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(1)LEGEND: H = logic high; L = logic low; X = don't care (either H or L).

(2)BA refers to the bank address pins (BA[2:0]).

SPRU970G – December 2005 – Revised June 2011

C6455/C6454 DDR2 Memory Controller

13

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Copyright © 2005–2011, Texas Instruments Incorporated

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Page 12 Page 14
Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map Pin Description DDR2 Memory Controller Signal DescriptionsTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsRefresh Command Refresh ModeActivation Actv Actv CommandDeactivation Dcab and Deac Dcab CommandDeac Command DDR2 Read Command Read CommandMemory Width, Byte Alignment, and Endianness Write WRT CommandAddressable Memory Ranges Address Type Generated by DDR2Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level DescriptionReset Considerations Self-Refresh ModeDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated byDDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc FieldSdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationDmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionOffset DDR2 Memory Controller RegistersRegister Description Module ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrBit Field Value Description Ifrdy DDR2 Memory Controller Status Register DmcstatSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcSdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC TrrdUsing this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Txsnr Txsrd Trtp TckeBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History DSP Products ApplicationsRfid TI E2E Community Home
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