Texas Instruments TMS320C6455 manual Self-Refresh Mode, Reset Considerations

Page 28

Peripheral Architecture

www.ti.com

2.9Self-Refresh Mode

Setting the self refresh (SR) bit in the SDRAM refresh control register (SDRFC) to 1 forces the DDR2 memory controller to place the external DDR2 SDRAM in a low-power mode (self refresh), in which the DDR2 SDRAM maintains valid data while consuming a minimal amount of power. When the SR bit is asserted, the DDR2 memory controller continues normal operation until all outstanding memory access requests have been serviced and the refresh backlog has been cleared. At this point, all open pages of DDR2 SDRAM are closed and a self-refresh (SLFRFR) command (an autorefresh command with DSDCKE low) is issued.

The DDR2 memory controller exits the self-refresh state when a memory access is received or when the SR bit in SDRFC is cleared. While in the self-refresh state, if a request for a memory access is received, the DDR2 memory controller services the memory access request, returning to the self-refresh state upon completion.

The DDR2 memory controller will not exit the self-refresh state (whether from a memory access request or from clearing the SR bit) until T_CKE + 1 cycles have expired since the self-refresh command was issued. The value of T_CKE is defined in the SDRAM timing 2 register (SDTIM2).

After exiting from the self-refresh state, the DDR2 memory controller will not immediately start using commands. Instead, it will wait T_XSNR+1 clock cycles before issuing non-read commands and T_XSRD+1 clock cycles before issuing read commands. The SDRAM timing 2 register (SDTIM2) programs the values of T_XSNR+1 and T_XSRD+1.

2.10Reset Considerations

The DDR2 memory controller can be reset through a hard reset or a soft reset. A hard reset resets the state machine, the FIFOs, and the internal registers. A soft reset only resets the state machine and the FIFOs. A soft reset does not reset the internal registers except for the interrupt registers. Register accesses cannot be performed while either reset is asserted.

The DDR2 memory controller hard and soft reset are derived from device-level resets. C6455/C6454 devices have several types of device-level resets: power-on reset, warm reset, max reset, system reset, and CPU reset. Table 8 shows the relationship between the device-level resets and the DDR2 memory controller resets.

Table 8. Device and DDR2 Memory Controller Reset Relationship

DDR2 Memory

 

 

Controller Reset

Effect

Initiated by:

 

 

 

Hard reset

Resets control logic and all DDR2 memory

Power on reset

 

controller registers

Warm reset

 

 

Max reset

Soft reset

Resets control logic and interrupt registers

System reset

 

 

CPU reset

 

 

 

In case of a warm reset on the DSP, the DDR2 SDRAM memory content can be retained if the user places the DDR2 SDRAM in self-refresh mode before invoking the warm reset. However, the DDR2 memory controller registers will be reset and need to be reprogrammed to the required values after the warm reset. For more information on the device-level resets, see the device-specific data manual.

2.11 DDR2 SDRAM Memory Initialization

DDR2 SDRAM devices contain mode and extended mode registers that configure the mode of operation for the device. These registers control parameters such as burst type, burst length, and CAS latency. The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands during the initialization sequence described in Section 2.11.2 and Section 2.11.3. The initialization sequence performed by the DDR2 memory controller is compliant with the JESDEC79-2A specification.

The DDR2 memory controller performs the initialization sequence under the following conditions:

•Automatically following a hard or soft reset, see Section 2.11.2.

28

C6455/C6454 DDR2 Memory Controller

SPRU970G – December 2005 – Revised June 2011

 

 

Submit Documentation Feedback

Copyright © 2005–2011, Texas Instruments Incorporated

Page 27 Page 29
Image 28
Page 27 Page 29
Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map DDR2 Memory Controller Signal Descriptions Pin DescriptionDDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol DescriptionsMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandRefresh Mode Refresh CommandActv Command Activation ActvDcab Command Deactivation Dcab and DeacDeac Command Read Command DDR2 Read CommandWrite WRT Command Memory Width, Byte Alignment, and EndiannessAddressable Memory Ranges Address Type Generated by DDR2Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Scheduling Possible Race ConditionRefresh Urgency Levels Urgency Level DescriptionSelf-Refresh Mode Reset ConsiderationsDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated by11.1 DDR2 Sdram Device Mode Register Configuration Values DDR2 Sdram Mode Register ConfigurationDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field11.2 DDR2 Sdram Initialization After Reset 11.3 DDR2 Sdram Initialization After Register ConfigurationInterrupt Support Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Configuration Register Sdcfg Sdcfg ConfigurationProgramming the Sdram Refresh Control Register Sdrfc FieldDDR2 Memory Refresh Specification Sdrfc ConfigurationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationSDTIM2 Configuration Dmcctl ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionOffset DDR2 Memory Controller RegistersRegister Description Module ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrBit Field Value Description DDR2 Memory Controller Status Register Dmcstat IfrdySdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsSdram Timing 1 Register SDTIM1 Sdram Timing 1 Register SDTIM1 Field DescriptionsTrfc TRP Trcd TWR Tras TRC TrrdUsing this formula Sdram Timing 2 Register SDTIM2 Sdram Timing 2 Register SDTIM2 Field DescriptionsTodt Txsnr Txsrd Trtp TckeBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register DmcctlRevision History Products Applications DSPRfid TI E2E Community Home
Top Page Image Contents