Texas Instruments TMS320C6747 DSP manual HC Interrupt Enable Register Hcinterruptenable, Mie

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Registers

3.5HC Interrupt Enable Register (HCINTERRUPTENABLE)

The HC interrupt enable register (HCINTERRUPTENABLE) enables various OHCI interrupt sources to generate interrupts to the level 2 interrupt controller. HCINTERRUPTENABLE is shown in Figure 6 and described in Table 6.

Figure 6. HC Interrupt Enable Register (HCINTERRUPTENABLE)

31	30	29								16
MIE	OC			Reserved
R/W1S-0 R-0				R-0
15			7	6	5	4	3	2	1	0
		Reserved		RHSC	FNO	UE	RD	SF	WDH	SO
		R-0		R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0
LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing 0 has no effect); -n= value after reset

		Table 6. HC Interrupt Enable Register (HCINTERRUPTENABLE) Field Descriptions
Bit	Field	Value Description
31	MIE	Master interrupt enable. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the
		corresponding bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.

0OHCI interrupt sources are ignored and USB host controller interrupts are not propagated to the level 2 interrupt controller.

		1	Allows other enabled OHCI interrupt sources to propagate to the level 2 interrupt controller.
30	OC	0-1	Ownership change.
29-7	Reserved	0	Reserved
6	RHSC		Root hub status change. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the
			corresponding bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
		0	Root hub status change interrupts do not propagate.
		1	When MIE is 1, allows root hub status change interrupts to propagate to the level 2 interrupt controller.
5	FNO		Frame number overflow. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the
			corresponding bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
		0	Frame number overflow interrupts do not propagate.
		1	When MIE is 1, allows frame number overflow interrupts to propagate to the level 2 interrupt controller.
4	UE		Unrecoverable error. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the
			corresponding bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
		0	Unrecoverable error interrupts do not propagate.
		1	When MIE is 1, allows unrecoverable error interrupts to propagate to the level 2 interrupt controller.
3	RD		Resume detected. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the corresponding
			bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
		0	Resume detected interrupts do not propagate.
		1	When MIE is 1, allows resume detected interrupts to propagate to the level 2 interrupt controller.
2	SF		Start of frame. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the corresponding bit in
			the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
		0	Start of frame interrupts do not propagate.
		1	When MIE is 1, allows start of frame interrupts to propagate to the level 2 interrupt controller.
1	WDH		Write done head. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the corresponding
			bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
		0	Write done head interrupts do not propagate.
		1	When MIE is 1, allows write done head interrupts to propagate to the level 2 interrupt controller.
0	SO		Scheduling overrun. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the corresponding
			bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
		0	Scheduling overrun interrupts do not propagate.
		1	When MIE is 1, allows scheduling overrun interrupts to propagate to the level 2 interrupt controller.
SPRUFM8–September 2008			Universal Serial Bus OHCI Host Controller	17
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Contents Literature Number SPRUFM8 September Users GuideSPRUFM8-September Contents List of Figures List of Tables Read This First Purpose of the Peripheral Universal Serial Bus Ohci Host Controller2 USB1 Module Local Bus Clock and Local Reset USB1 Module Clock and ResetInternal System Bus Clocks Needed by the USB1 Module 3 USB1 Module Bus 48-MHz Reference ClockUSB1 Module Open Host Controller Interface Functionality USB1 Module Differences From Ohci Specification for USBOhci USB Suspend State Implementation of Ohci Specification for USBOhci Interrupts USB Host Controller Access to System MemoryPhysical Addressing MMUUSB Host Controller Registers Ohci Revision Number Register Hcrevision HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision Field Descriptions REVPeriodic list enable Control list enableControl ED per bulk ED Control EDs per bulk EDSOC HC Command and Status Register HccommandstatusOCR BLF CLF HCR OCRRhsc HC Interrupt and Status Register HcinterruptstatusRhsc FNO WDH MIE HC Interrupt Enable Register HcinterruptenableHC Interrupt Disable Register Hcinterruptdisable HC Current Periodic Register Hcperiodcurrented HC Hcaa Address Register HchccaHC Hcaa Address Register Hchcca Field Descriptions HccaChed HC Head Control Register HccontrolheadedHC Head Control Register Hccontrolheaded Field Descriptions Controller HC Current Control Register HccontrolcurrentedCced HC Current Bulk Register Hcbulkcurrented HC Head Bulk Register HcbulkheadedHC Head Bulk Register Hcbulkheaded Field Descriptions HC Current Bulk Register Hcbulkcurrented Field DescriptionsHC Frame Interval Register Hcfminterval HC Head Done Register HcdoneheadHC Head Done Register Hcdonehead Field Descriptions HC Frame Interval Register Hcfminterval Field DescriptionsHC Frame Number Register Hcfmnumber HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber Field Descriptions FRTHC Periodic Start Register Hcperiodicstart HC Periodic Start Register HcperiodicstartLST HC Low-Speed Threshold Register Hclsthreshold628h Reserved 13-0HC Root Hub a Register Hcrhdescriptora Field Descriptions HC Root Hub a Register HcrhdescriptoraPotpg Nocp Ocpm NPS PSM NDPHC Root Hub B Register Hcrhdescriptorb Field Descriptions HC Root Hub B Register HcrhdescriptorbPPCM3 PPCM2 PPCM1 PPCM0 PPCM3HC Root Hub Status Register Hcrhstatus Field Descriptions HC Root Hub Status Register HcrhstatusHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR Effect Port 2 current connect status has not changed HC Port 2 Status and Control Register HCRHPORTSTATUS2Begin signaling USB reset to port When read as 0, USB reset is not being sent to portEnd of the USB reset sequence Write of 1 to this bit clears the port 2 port enable bitRfid DSP