Texas Instruments TMS320C6747 DSP manual HC Head Bulk Register Hcbulkheaded

Page 22

Registers

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3.11 HC Head Bulk Register (HCBULKHEADED)

The HC head bulk register (HCBULKHEADED) defines the physical address of the head endpoint descriptor (ED) on the bulk ED list. HCBULKHEADED is shown in Figure 12 and described in Table 12.

Figure 12. HC Head Bulk Register (HCBULKHEADED)

31			16
	BHED
	R/W-0
15	4	3	0
BHED			Reserved
R/W-0			R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 12. HC Head Bulk Register (HCBULKHEADED) Field Descriptions

Bit	Field	Value	Description
31-4	BHED	0-FFF FFFFh	Physical address of the head ED on the bulk ED list. This field represents bits 31-4 of the physical
			address of the head ED on the bulk ED list. EDs are assumed to begin on a 16-byte aligned
			address, so bits 3-0 of this pointer are assumed to be 0. For the restrictions on physical
			addresses, see Section 2.7.
3-0	Reserved	0	Reserved

3.12 HC Current Bulk Register (HCBULKCURRENTED)

The HC current bulk register (HCBULKCURRENTED) defines the physical address of the next endpoint descriptor (ED) on the bulk ED list. HCBULKCURRENTED is shown in Figure 13 and described in Table 13.

Figure 13. HC Current Bulk Register (HCBULKCURRENTED)

31			16
	BCED
	R/W-0
15	4	3	0
BCED			Reserved
R/W-0			R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 13. HC Current Bulk Register (HCBULKCURRENTED) Field Descriptions

Bit	Field	Value	Description
31-4	BCED	0-FFF FFFFh	Physical address of the current ED on the bulk ED list. This field represents bits 31-4 of the
			physical address of the next ED on the bulk ED list. EDs are assumed to begin on a 16-byte
			aligned address, so bits 3-0 of this pointer are assumed to be 0. For the restrictions on physical
			addresses, see Section 2.7.
			A value of 0 indicates that the USB host controller has reached the end of the bulk ED list without
			finding any transfers to process. This register is automatically updated by the USB host controller.
3-0	Reserved	0	Reserved
22	Universal Serial Bus OHCI Host Controller			SPRUFM8–September 2008

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Contents Users Guide Literature Number SPRUFM8 SeptemberSPRUFM8-September Contents List of Figures List of Tables Read This First Universal Serial Bus Ohci Host Controller Purpose of the PeripheralInternal System Bus Clocks Needed by the USB1 Module USB1 Module Clock and Reset2 USB1 Module Local Bus Clock and Local Reset 3 USB1 Module Bus 48-MHz Reference ClockUSB1 Module Differences From Ohci Specification for USB USB1 Module Open Host Controller Interface FunctionalityImplementation of Ohci Specification for USB Ohci USB Suspend StatePhysical Addressing USB Host Controller Access to System MemoryOhci Interrupts MMUUSB Host Controller Registers Ohci Revision Number Register Hcrevision Field Descriptions HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision REVControl ED per bulk ED Control list enablePeriodic list enable Control EDs per bulk EDOCR BLF CLF HCR HC Command and Status Register HccommandstatusSOC OCRRhsc FNO WDH HC Interrupt and Status Register HcinterruptstatusRhsc HC Interrupt Enable Register Hcinterruptenable MIEHC Interrupt Disable Register Hcinterruptdisable HC Hcaa Address Register Hchcca Field Descriptions HC Hcaa Address Register HchccaHC Current Periodic Register Hcperiodcurrented HccaHC Head Control Register Hccontrolheaded Field Descriptions HC Head Control Register HccontrolheadedChed Cced HC Current Control Register HccontrolcurrentedController HC Head Bulk Register Hcbulkheaded Field Descriptions HC Head Bulk Register HcbulkheadedHC Current Bulk Register Hcbulkcurrented HC Current Bulk Register Hcbulkcurrented Field DescriptionsHC Head Done Register Hcdonehead Field Descriptions HC Head Done Register HcdoneheadHC Frame Interval Register Hcfminterval HC Frame Interval Register Hcfminterval Field DescriptionsHC Frame Number Register Hcfmnumber Field Descriptions HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber FRTHC Periodic Start Register Hcperiodicstart HC Periodic Start Register Hcperiodicstart628h HC Low-Speed Threshold Register HclsthresholdLST Reserved 13-0Potpg HC Root Hub a Register HcrhdescriptoraHC Root Hub a Register Hcrhdescriptora Field Descriptions Nocp Ocpm NPS PSM NDPPPCM3 PPCM2 PPCM1 PPCM0 HC Root Hub B Register HcrhdescriptorbHC Root Hub B Register Hcrhdescriptorb Field Descriptions PPCM3HC Root Hub Status Register Hcrhstatus HC Root Hub Status Register Hcrhstatus Field DescriptionsHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR HC Port 2 Status and Control Register HCRHPORTSTATUS2 Effect Port 2 current connect status has not changedEnd of the USB reset sequence When read as 0, USB reset is not being sent to portBegin signaling USB reset to port Write of 1 to this bit clears the port 2 port enable bitDSP Rfid