Texas Instruments TMS320C6747 DSP manual HC Port 2 Status and Control Register HCRHPORTSTATUS2

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Registers

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3.23 HC Port 2 Status and Control Register (HCRHPORTSTATUS2)

The HC port 2 status and control register (HCRHPORTSTATUS2) reports and controls the state of USB host port 2. HCRHPORTSTATUS2 is shown in Figure 24 and described in Table 24.

Figure 24. HC Port 2 Status and Control Register (HCRHPORTSTATUS2)

31						21	20	19	18	17	16
			Reserved				PRSC	OCIC	PSSC	PESC	CSC
			R-0				R/W1C-0	R/W-0	R/W1C-0 R/W1C-0		R/W-0
15							10		9	8
			Reserved					LSDA/CPP		PPS/SPP
			R-0					R/W-0		R/W-1
7			5	4	3		2		1	0
	Reserved			PRS/SPR	POCI/CSS	PSS/SPS		PES/SPE		CCS/CPE
	R-0			R/W-0	R/W-0		R/W-0	R/W-0		R/W-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n= value after reset
	Table 24. HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Field Descriptions
Bit	Field	Value	Description
31-21	Reserved	0	Reserved
20	PRSC		Port 2 reset status change. A write of 1 clears this bit; a write of 0 has no effect.
		0	Port 2 port reset status bit has not changed.
		1	Port 2 port reset status bit has changed.
19	OCIC	0	Port 2 overcurrent indicator change. Because the device does not provide inputs for signaling
			external overcurrent indication to the USB host controller, this bit is always 0. Overcurrent
			monitoring, if required, must be handled through some other mechanism. This bit has no
			relationship to the OTG controller register bits that relate to VBUS.
18	PSSC		Port 2 suspend status changed. A write of 1 clears this bit; a write of 0 has no effect.
		0	Port 2 port suspend status has not changed.
		1	Port 2 port suspend status has changed. Suspend status is considered to have changed only after
			the resume pulse, low-speed EOP, and 3-ms synchronization delays have been completed.
17	PESC		Port 2 enable status change. A write of 1 clears this bit; a write of 0 has no effect.
		0	Port 2 port enable status has not changed.
		1	Port 2 port enable status has changed.
16	CSC		Port 2 connect status change. If the DR[2] bit in the HC root hub B register (HCRHDESCRIPTORB)
			is set to 1 to indicate a nonremovable USB device on port 2, this bit is set only after a root hub
			reset to inform the system that the device is attached. A write of 1 clears this bit; a write of 0 has no
			effect.
		0	Port 2 current connect status has not changed.
		1	Port 2 current connect status has changed due to a connect or disconnect event. If current connect
			status is 0 when a set port reset, set port enable, or set port suspend write occurs, then this bit is
			set.
15-10	Reserved	0	Reserved
9	LSDA/CPP		Port 2 low-speed device attached/clear port power. This bit indicates, when read as 1, that a
			low-speed device is attached to port 2. A 0 in this bit indicates a full-speed device. This bit is valid
			only when port 2 current connect status is 1. The USB host controller does not control external port
			power using OHCI mechanisms, so, if required, USB host port power must be controlled through
			other means.
		0	A write of 0 to this bit has no effect.
		1	The host controller driver can write a 1 to this bit to clear the port 2 port power status.

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Universal Serial Bus OHCI Host Controller

SPRUFM8–September 2008

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Contents Users Guide Literature Number SPRUFM8 SeptemberSPRUFM8-September Contents List of Figures List of Tables Read This First Universal Serial Bus Ohci Host Controller Purpose of the PeripheralUSB1 Module Clock and Reset 2 USB1 Module Local Bus Clock and Local ResetInternal System Bus Clocks Needed by the USB1 Module 3 USB1 Module Bus 48-MHz Reference ClockUSB1 Module Differences From Ohci Specification for USB USB1 Module Open Host Controller Interface FunctionalityImplementation of Ohci Specification for USB Ohci USB Suspend StateUSB Host Controller Access to System Memory Ohci InterruptsPhysical Addressing MMUUSB Host Controller Registers HC Operating Mode Register Hccontrol Ohci Revision Number Register HcrevisionOhci Revision Number Register Hcrevision Field Descriptions REVControl list enable Periodic list enableControl ED per bulk ED Control EDs per bulk EDHC Command and Status Register Hccommandstatus SOCOCR BLF CLF HCR OCRRhsc HC Interrupt and Status Register HcinterruptstatusRhsc FNO WDH HC Interrupt Enable Register Hcinterruptenable MIEHC Interrupt Disable Register Hcinterruptdisable HC Hcaa Address Register Hchcca HC Current Periodic Register HcperiodcurrentedHC Hcaa Address Register Hchcca Field Descriptions HccaChed HC Head Control Register HccontrolheadedHC Head Control Register Hccontrolheaded Field Descriptions Controller HC Current Control Register HccontrolcurrentedCced HC Head Bulk Register Hcbulkheaded HC Current Bulk Register HcbulkcurrentedHC Head Bulk Register Hcbulkheaded Field Descriptions HC Current Bulk Register Hcbulkcurrented Field DescriptionsHC Head Done Register Hcdonehead HC Frame Interval Register HcfmintervalHC Head Done Register Hcdonehead Field Descriptions HC Frame Interval Register Hcfminterval Field DescriptionsHC Frame Remaining Register Hcfmremaining HC Frame Number Register HcfmnumberHC Frame Number Register Hcfmnumber Field Descriptions FRTHC Periodic Start Register Hcperiodicstart HC Periodic Start Register HcperiodicstartHC Low-Speed Threshold Register Hclsthreshold LST628h Reserved 13-0HC Root Hub a Register Hcrhdescriptora HC Root Hub a Register Hcrhdescriptora Field DescriptionsPotpg Nocp Ocpm NPS PSM NDPHC Root Hub B Register Hcrhdescriptorb HC Root Hub B Register Hcrhdescriptorb Field DescriptionsPPCM3 PPCM2 PPCM1 PPCM0 PPCM3HC Root Hub Status Register Hcrhstatus HC Root Hub Status Register Hcrhstatus Field DescriptionsHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR HC Port 2 Status and Control Register HCRHPORTSTATUS2 Effect Port 2 current connect status has not changedWhen read as 0, USB reset is not being sent to port Begin signaling USB reset to portEnd of the USB reset sequence Write of 1 to this bit clears the port 2 port enable bitDSP Rfid