Texas Instruments TMS320C6747 DSP manual HC Periodic Start Register Hcperiodicstart

Page 25

www.ti.com

Registers

3.17 HC Periodic Start Register (HCPERIODICSTART)

The HC periodic start register (HCPERIODICSTART) defines the position within the USB frame where endpoint descriptors (EDs) on the periodic list have priority over EDs on the bulk and control lists. HCPERIODICSTART is shown in Figure 18 and described in Table 18.

			Figure 18. HC Periodic Start Register (HCPERIODICSTART)
31			16
			Reserved
			R-0
15	14	13	0
Reserved			PS
	R-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 18. HC Periodic Start Register (HCPERIODICSTART) Field Descriptions

Bit	Field	Value	Description
31-14	Reserved	0	Reserved
13-0	PS	0-3FFFh	Periodic start. The host controller driver must program this value to be about 10% less than the
			frame interval (FI) value in the HC frame interval register (HCFMINTERVAL), so that control and
			bulk EDs have priority for the first 10% of the frame; then periodic EDs have priority for the
			remaining 90% of the frame.

SPRUFM8–September 2008	Universal Serial Bus OHCI Host Controller	25
Submit Documentation Feedback

Image 25

Contents Literature Number SPRUFM8 September Users GuideSPRUFM8-September Contents List of Figures List of Tables Read This First Purpose of the Peripheral Universal Serial Bus Ohci Host Controller2 USB1 Module Local Bus Clock and Local Reset USB1 Module Clock and ResetInternal System Bus Clocks Needed by the USB1 Module 3 USB1 Module Bus 48-MHz Reference ClockUSB1 Module Open Host Controller Interface Functionality USB1 Module Differences From Ohci Specification for USBOhci USB Suspend State Implementation of Ohci Specification for USBOhci Interrupts USB Host Controller Access to System MemoryPhysical Addressing MMUUSB Host Controller Registers Ohci Revision Number Register Hcrevision HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision Field Descriptions REVPeriodic list enable Control list enableControl ED per bulk ED Control EDs per bulk EDSOC HC Command and Status Register HccommandstatusOCR BLF CLF HCR OCRRhsc FNO WDH HC Interrupt and Status Register HcinterruptstatusRhsc MIE HC Interrupt Enable Register HcinterruptenableHC Interrupt Disable Register Hcinterruptdisable HC Current Periodic Register Hcperiodcurrented HC Hcaa Address Register HchccaHC Hcaa Address Register Hchcca Field Descriptions HccaHC Head Control Register Hccontrolheaded Field Descriptions HC Head Control Register HccontrolheadedChed Cced HC Current Control Register HccontrolcurrentedController HC Current Bulk Register Hcbulkcurrented HC Head Bulk Register HcbulkheadedHC Head Bulk Register Hcbulkheaded Field Descriptions HC Current Bulk Register Hcbulkcurrented Field DescriptionsHC Frame Interval Register Hcfminterval HC Head Done Register HcdoneheadHC Head Done Register Hcdonehead Field Descriptions HC Frame Interval Register Hcfminterval Field DescriptionsHC Frame Number Register Hcfmnumber HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber Field Descriptions FRTHC Periodic Start Register Hcperiodicstart HC Periodic Start Register HcperiodicstartLST HC Low-Speed Threshold Register Hclsthreshold628h Reserved 13-0HC Root Hub a Register Hcrhdescriptora Field Descriptions HC Root Hub a Register HcrhdescriptoraPotpg Nocp Ocpm NPS PSM NDPHC Root Hub B Register Hcrhdescriptorb Field Descriptions HC Root Hub B Register HcrhdescriptorbPPCM3 PPCM2 PPCM1 PPCM0 PPCM3HC Root Hub Status Register Hcrhstatus Field Descriptions HC Root Hub Status Register HcrhstatusHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR Effect Port 2 current connect status has not changed HC Port 2 Status and Control Register HCRHPORTSTATUS2Begin signaling USB reset to port When read as 0, USB reset is not being sent to portEnd of the USB reset sequence Write of 1 to this bit clears the port 2 port enable bitRfid DSP