Texas Instruments TMS320C6747 DSP manual Implementation of Ohci Specification for USB

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Architecture

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2.4Implementation of OHCI Specification for USB

2.4.1USB Host Controller Endpoint Descriptor (ED) List Head Pointers

The OHCI Specification for USB provides a specific sequence of operations for the host controller driver to perform when setting up the host controller. Failure to follow that sequence can result in malfunction. As a specific example, the HCCONTROLHEADED and HCBULKHEADED pointer registers and the 32 HCCAINTERRUPTTABLE pointers must all point to valid physical addresses of valid endpoint descriptors.

The USB host controller does not check HCCONTROLHEADED registers, HCBULKHEADED registers, or the values in the 32 HCCAINTERRUPTTABLE pointers before using them to access EDs. In particular if any of these pointers are NULL when the corresponding list enable bit is set, the USB host controller attempts to access using the physical address of 0, which is not a valid memory region for the USB controller to access.

2.4.2OHCI USB Suspend State

The USB host controller ignores upstream traffic from downstream devices for about 3 ms after the host controller state (HCCONTROL.HCFS) changes from USB resume state to USB operational state. If any TDs cause generation of downstream packets during that time, the downstream packets are sent, but downstream device responses are ignored. Any such TDs are aborted with completion codes marked as Device Not Responding. TDs on any of the lists (periodic, control, bulk, and isochronous) can cause such an occurrence.

The USB specification requires that system software must provide a 10-ms resume recovery time (TRSMRCY) after a bus segment transitions from resume signaling to normal operational mode. During that time, only start of frame packets are to be sent on the bus segment. The system software should disable all list enable bits (HCCONTROL.PLE, HCCONTROL.IE, HCCONTROL.CLE, and HCCONTROL.BLE) and then wait for at least 1 ms before setting the host controller into USB suspend state (via HCCONTROL.HCFS). When restoring from suspend, system software must set the host controller into USB resume state, and wait for the host controller to transition into USB operational state. System software must then wait 10 ms before enabling the host controller list enable bits.

When the host controller has been placed into the USB suspend state under software control, but is brought out by a remote wake-up, system software must monitor the HCRHPORTSTATUS[x].PSS and HCRHPORTSTATUS[x].PSSC bits. The HCRHPORTSTATUS[x].PSS bit changes to 0 only after completion of resume signaling on the bus segment, and completion of the 3-ms period (packets from downstream devices are ignored).

When using port-specific suspend, it is not necessary to disable the host controller lists, as long as there are no active EDs and TDs directed toward devices that are downstream of the suspended port. For port-specific suspend operations, the host controller does not issue a root hub status change interrupt (HCRHPORTSTATUS[n].PSSC bit = 1 and HCRHPORTSTATUS[n].PSS = 0), until the end of the approximately 3-ms delay after the resume signaling completes.

When using port-specific suspend, system software must ensure that there are no active EDs for devices that are downstream of the suspended port before setting the port into suspend mode. While the port is in suspend or being resumed, system software must not enable any EDs for any devices downstream of the suspended port. Once the root hub status change interrupt occurs as a result of the suspended port PSS bit changing to 0, EDs can be enabled for devices downstream of the operational port.

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Universal Serial Bus OHCI Host Controller

SPRUFM8–September 2008

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Contents Users Guide Literature Number SPRUFM8 SeptemberSPRUFM8-September Contents List of Figures List of Tables Read This First Universal Serial Bus Ohci Host Controller Purpose of the PeripheralInternal System Bus Clocks Needed by the USB1 Module USB1 Module Clock and Reset2 USB1 Module Local Bus Clock and Local Reset 3 USB1 Module Bus 48-MHz Reference ClockUSB1 Module Differences From Ohci Specification for USB USB1 Module Open Host Controller Interface FunctionalityImplementation of Ohci Specification for USB Ohci USB Suspend StatePhysical Addressing USB Host Controller Access to System MemoryOhci Interrupts MMUUSB Host Controller Registers Ohci Revision Number Register Hcrevision Field Descriptions HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision REVControl ED per bulk ED Control list enablePeriodic list enable Control EDs per bulk EDOCR BLF CLF HCR HC Command and Status Register HccommandstatusSOC OCRRhsc FNO WDH HC Interrupt and Status Register HcinterruptstatusRhsc HC Interrupt Enable Register Hcinterruptenable MIEHC Interrupt Disable Register Hcinterruptdisable HC Hcaa Address Register Hchcca Field Descriptions HC Hcaa Address Register HchccaHC Current Periodic Register Hcperiodcurrented HccaHC Head Control Register Hccontrolheaded Field Descriptions HC Head Control Register HccontrolheadedChed Cced HC Current Control Register HccontrolcurrentedController HC Head Bulk Register Hcbulkheaded Field Descriptions HC Head Bulk Register HcbulkheadedHC Current Bulk Register Hcbulkcurrented HC Current Bulk Register Hcbulkcurrented Field DescriptionsHC Head Done Register Hcdonehead Field Descriptions HC Head Done Register HcdoneheadHC Frame Interval Register Hcfminterval HC Frame Interval Register Hcfminterval Field DescriptionsHC Frame Number Register Hcfmnumber Field Descriptions HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber FRTHC Periodic Start Register Hcperiodicstart HC Periodic Start Register Hcperiodicstart628h HC Low-Speed Threshold Register HclsthresholdLST Reserved 13-0Potpg HC Root Hub a Register HcrhdescriptoraHC Root Hub a Register Hcrhdescriptora Field Descriptions Nocp Ocpm NPS PSM NDPPPCM3 PPCM2 PPCM1 PPCM0 HC Root Hub B Register HcrhdescriptorbHC Root Hub B Register Hcrhdescriptorb Field Descriptions PPCM3HC Root Hub Status Register Hcrhstatus HC Root Hub Status Register Hcrhstatus Field DescriptionsHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR HC Port 2 Status and Control Register HCRHPORTSTATUS2 Effect Port 2 current connect status has not changedEnd of the USB reset sequence When read as 0, USB reset is not being sent to portBegin signaling USB reset to port Write of 1 to this bit clears the port 2 port enable bitDSP Rfid